This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.

UVM-based verification environment for a 5-stage RV32I RISC-V pipeline using constrained-random testing, DPI-C golden reference modeling, assertions, scoreboarding, functional coverage, and 20-seed QuestaSim regression debugging.

A Verilog-based five-stage pipelined processor with complete hazard handling (stalling, forwarding) and modular RTL design.

This repository contain all the necessary files to verify PISO Universal Register

The RTL implementation of a 8-bit pipelined signed integer multiplication module with some optimization techniques and testbench.

UVM + Formal Verification of SPI Protocol.

RTL design of Pipelined Heap component

C-DAC Final Project | RISC-V RV32I Subset Design and Verification with UVM

AXI4 Memory Controller UVM Verification Environment with real Siemens Questa seed-1 simulation logs, scoreboard checks, functional coverage summaries, and documented burst-read debug fix.

Repository of codes related to the Logic Circuit course at the University of Tehran.

A robust SystemVerilog implementation of a configurable Data Aligner module, accompanied by a comprehensive UVM (Universal Verification Methodology) testbench.