Popular repositories Loading

1. Low-Power-ALU-Clock-Gating Low-Power-ALU-Clock-Gating Public

   16-bit ALU with clock gating achieving 30-35% power reduction

   Verilog 1

2. AXI4-Lite-Master-Slave-Bus-Interface AXI4-Lite-Master-Slave-Bus-Interface Public

   Fully verified AXI4-Lite Master-Slave in Verilog HDL

   Verilog

3. low-power-16bit-alu-sv low-power-16bit-alu-sv Public

   SystemVerilog implementation of a 16-bit low-power ALU with assertion-based verification.

   SystemVerilog

4. spi-uvm-formal-verification spi-uvm-formal-verification Public

   UVM + Formal Verification of SPI Protocol.

   SystemVerilog