Register File

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The Register File

The Register File is the component responsible for managing the general-purpose registers of the processor. It stores the data used by most instructions. The file contains 32 registers, each with specific labels and functions as previously described. It also includes connections to the A, B, and C buses, along with an input for the addresses of the currently active registers.

The write signal of the Register File is active during the second phase of every instruction, except for store, branch, and load instructions. The load instruction is an exception, as its write phase is delayed by one cycle, as explained in Timing and Pipeline.

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Inside the Register File

In Logisim, the Register File is simply an encapsulation of the generic Register Bank. This design choice was made to allow reuse of the Register Bank for a future Floating-Point Register File, although this feature has not yet been implemented in the current version of DRISC-V.

The following image shows part of the circuit inside the Register Bank:

How the Circuit Works

• The C address is decoded into 32 signals, each corresponding to the write enable input of a register.
• The decoder is only activated if it receives a signal from the write input.
• When the clock transitions from 0 to 1 and the write signal is active, the selected register receives data from the C input.
• The output of each register is connected to two multiplexers:
  • One for the A bus
  • One for the B bus
• Each multiplexer receives an address to determine which register is selected for output.

SystemVerilog Code

`timescale 1s/1s
//inputs and outputs
module register_file(
    input clock,
    input reset,
    input write,
    input [4:0] a_address,
    input [4:0] b_address,
    input [4:0] c_address,
    input [31:0] c_in,
    output [31:0] a_out,
    output [31:0] b_out
);
//registers
    reg [31:0] registers [0:31];

    assign a_out = registers[a_address];
    assign b_out = registers[b_address];

    always @(posedge clock) begin
//sets all registers to 0.
        if (reset) begin
            integer i;
            for (i = 0; i < 32; i = i + 1) begin
                registers[i] <= 32'b0;
            end
        end
//in the system verilog version, instead of hardwiring the register x0 to 0, we just don't write to it
        else if (write && c_address != 5'd0) begin
            registers[c_address] <= c_in;
        end
    end

endmodule