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Welcome to the Didactic RISC-V Wiki!

In this manual, you'll find essential information about the inner workings of the architecture, along with detailed explanations of the various features available in the project.

To fully understand this project, it is recommended to have prior knowledge of digital systems, logic circuitry, and the fundamentals of computer architecture. This wiki does not provide comprehensive explanations of computer organization or architectural principles, so additional resources may be necessary for those unfamiliar with these topics.

That said, the documentation strives to maintain a didactic tone and aims to present architectural concepts and internal mechanisms as clearly and simply as possible, making it accessible even to those with limited background in the field.

📚 Wiki Overview

Below is a summary of the main sections available:

Architecture Overview

Details the internal structure of the DRISC-V processor, with a breakdown of its components and how they implement the RV32IM Zmmul Zicsr RISC-V specification. Includes a brief overview of available I/O devices.

The Simulation

Presents the graphical simulation models built in Logisim as well as the simulation environment implemented in SystemVerilog, including instructions on how to run, modify, and experiment with the architecture.

Assembler Guide

Describes how to use the custom C# assembler developed for this project, including steps to assemble programs and load them into the simulation environments.