CSR Controller

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The Control and Status Registers Controller

The Control and Status Registers (CSR) Controller is the largest component in DRISC-V. It is responsible for managing system instructions, storing CSRs, and handling interrupts and exceptions. Its implementation is optional, as it does not directly affect the execution of standard instructions.

The CSR Controller includes two interfaces for communication with the Operation Controller and the Program Counter. These interfaces provide essential data for detecting and handling exceptions within the system. The following table summarizes these connections:

Signal	Connects To	Input/Output	Description
Current Instruction	Operation Controller	Input	Serves as the Trap Value for certain exceptions. Parameters like funct3 are extracted from it.
Next Instruction	Operation Controller	Input	Decoded into system instructions and CSR addresses.
Next Decoded Instruction	Operation Controller	Input	Used to verify if the next opcode is valid or a system instruction.
Load, Store, and Jump	Operation Controller	Input	Triggers misalignment exceptions caused by these instructions.
Exception	Operation Controller	Output	Signals that an exception has occurred.
Next System Load	Operation Controller	Output	Used to load CSRs mapped in external memory, prompting a load instruction.
System Jump	Operation Controller and Program Counter	Output	Signals a jump using the System Target Address.
System Load	Program Counter	Output	Signals the PC to use the System Target Address for loading.
Calculated Address	Program Counter	Input	Contains the address calculated by the PC for jumps and load/store operations.
System Target Address	Program Counter	Output	Contains the address used for system jumps and loads.

In addition to these connections, the CSR Controller also interfaces with the A and C Buses for CSR manipulation instructions. It receives inputs for the Phase and Interrupt signals as well.

You can see in the image of the component that it contains the value of most CSRs listed in the (Available ISA Page)[./available-instruction-set#machine-level-csrs-and-counters]. Not all are 32 bit, and the reason for that is that not all bits are necessary to be stored, and instead can be hardwired to zero. The CSRs that are not present aren't obtained through registers, and those are the mip, that is obtained through the the interrupt signals inputs, and the time CSR, which is mapped in memory and obtained from an external device.

CSR Controller Behavior.

Before looking how the circuit is configured internaly it is important to understand the logic of what is happening.

The CSR Controller can be devided into a synchronous and a asynchronous routine.

Synchronous Routine

If system is in reset state:
    Initialize all registers with their default values

Else if system is in phase 2:
    If there is an interrupt OR an exception:
        Execute the trap handling routine
    Else if the instruction is MRET:
        Execute the MRET routine
    Else if the instruction is a CSR operation AND the CSR is valid:
        Update the selected CSR with the newly calculated value

    If there is NO exception:
        Increment the instruction counter (INSTRET = INSTRET + 1)

Else if system is in phase 1 AND the instruction is a CSR operation AND the CSR is valid:
    Set bus C to the value of the selected register

If system is NOT in reset state:
    Increment the cycle counter (CYCLE = CYCLE + 1)

Function that calculates new CSR Values

Inputs: Register, Data  
Output: New CSR value

If the operation mode is "write":
    Return Data

Else if the operation mode is "set":
    Return (Register OR Data)

Else if the operation mode is "clear":
    Return (Register AND NOT Data)

Else: Return no value

Asynchronous Routine

Initialize asynchronous signals:
    Interrupt ← FALSE
    Exception ← FALSE
    Cause ← None
    Value ← 0

If interrupts are enabled OR system is in User Mode:
    If interrupt X is enabled AND pending:
        Interrupt ← TRUE
        Cause ← Interrupt X

If Interrupt is TRUE:
    If MTVEC is in vectored mode:
        Target Address ← MTVEC + (Cause × 4)
    Else:
        Target Address ← MTVEC

Else if any exception condition is TRUE:
    Exception ← TRUE
    Cause ← Exception code
    Value ← Current instruction, calculated address, or 0

Else if instruction is MRET:
    Target Address ← MEPC

If Exception is TRUE:
    Target Address ← MTVEC

Inside the CSR Controller

The CSR Controller can be divided into multiple parts.