Respect routed via layer spans

[seveibar]

Summary

• materialize routed pcb_via.layers from each route point's from_layer and to_layer instead of expanding every via across the full board stack
• use the same physical span for phased-autorouting via obstacles
• update the existing blind-via, copper-pour, ten-layer, and fanout-plane expectations

Why

The fanout solver already emits correct plane drops such as top -> inner1 and top -> inner2. Core was preserving those endpoint fields but setting pcb_via.layers to every board layer. That made DRC and later routing treat blind plane drops as through-vias, causing false collisions on signal layers beyond the via's physical span.

This surfaced in the RK3326 fanout as 15 USB-to-supply-via DRC errors on inner3 even though its 205 supply vias terminate on inner1 or inner2.

Scope

This is intentionally separate from the fanout plane-inference change in #2929. It changes two production call sites and only the existing expectations that encoded full-stack vias.

Validation

• focused routed-via, copper-pour, ten-layer, and fanout-plane tests: 5 passed, 0 failed
• full CI shard 3: 311 passed, 0 failed
• full CI shard 4: 305 passed, 0 failed
• bunx tsc --noEmit
• bun run build
• RK3326 end-to-end build against this branch: zero circuit errors; 154 top -> inner1 ground drops and 51 top -> inner2 power drops
• RK3326 footprint/fanout validator passes

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Project	Deployment	Actions	Updated (UTC)
tscircuit-core-benchmarks	Ready	Preview	Jul 30, 2026 10:08pm

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Impact: Major

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