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Merged
Minty-Meeo merged 10 commits into from
Jun 26, 2026
Merged

Some more bugfixes, documentation, and annotations #203

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a59914e
Nitpicks
Minty-Meeo Jun 26, 2026
23f366b
Bugfixes
Minty-Meeo Jun 26, 2026
441bba0
Use PPCArch.h macros for mfspr/mtspr
Minty-Meeo Jun 23, 2026
8efd413
Document hw_regs magic numbers
Minty-Meeo Jun 23, 2026
a5178be
Document DVD magic numbers
Minty-Meeo Jun 23, 2026
0db0a74
Rename parameters in CARDBios.c to `chan`
Minty-Meeo Jun 23, 2026
d56963b
Remove hungarian notation from POD GX structs
Minty-Meeo Jun 23, 2026
066dd61
Give `StdSystem::openFile` default parameter arguments
Minty-Meeo Jun 23, 2026
b0034bc
Fix illegal pointers to member functions
Minty-Meeo Jun 23, 2026
8152e99
Create and implement `stack_new` macro
Minty-Meeo Jun 24, 2026
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61 changes: 26 additions & 35 deletions include/Dolphin/GX/GXData.h
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Original file line number Diff line number Diff line change
Expand Up @@ -132,27 +132,14 @@ extern struct __GXData_struct* gx;
////////////////////////////////////////////

///////////// REGISTER DEFINES /////////////
// Declare registers.
extern u16* __cpReg;
extern u32* __piReg;
extern u16* __memReg;
extern u16* __peReg;

// Define register addresses.
#define GX_CP_ADDR (0x0C000000)
#define GX_PE_ADDR (0x0C001000)
#define GX_PI_ADDR (0x0C003000)
#define GX_MEM_ADDR (0x0C004000)

#define GX_GET_MEM_REG(offset) (*(vu16*)((vu16*)(__memReg) + (offset)))
#define GX_GET_CP_REG(offset) (*(vu16*)((vu16*)(__cpReg) + (offset)))
#define GX_GET_PE_REG(offset) (*(vu16*)((vu16*)(__peReg) + (offset)))
#define GX_GET_PI_REG(offset) (*(vu32*)((vu32*)(__piReg) + (offset)))

#define GX_SET_MEM_REG(offset, val) (*(vu16*)((vu16*)(__memReg) + (offset)) = val)
#define GX_SET_CP_REG(offset, val) (*(vu16*)((vu16*)(__cpReg) + (offset)) = val)
#define GX_SET_PE_REG(offset, val) (*(vu16*)((vu16*)(__peReg) + (offset)) = val)
#define GX_SET_PI_REG(offset, val) (*(vu32*)((vu32*)(__piReg) + (offset)) = val)

// In GX, these hardware registers are commonly accessed through these variables rather than what is defined in "hw_regs.h".
// NOTE: DWARF info lists all of these as "void *", but these types make more sense.
extern vu16* __cpReg;
extern vu32* __piReg;
extern vu16* __memReg;
extern vu16* __peReg;

#define VERIF_RAS_REG(value) (__gxVerif->rasRegs[((value) & 0xFF000000) >> 24] = value)

#define GX_WRITE_RAS_REG(value) \
Expand Down Expand Up @@ -226,11 +213,11 @@ extern u16* __peReg;
static inline u32 GXReadMEMReg(u32 addrLo, u32 addrHi)
{
u32 hiStart, hiNew, lo;
hiStart = GX_GET_MEM_REG(addrHi);
hiStart = __memReg[addrHi];
do {
hiNew = hiStart;
lo = GX_GET_MEM_REG(addrLo);
hiStart = GX_GET_MEM_REG(addrHi);
lo = __memReg[addrLo];
hiStart = __memReg[addrHi];
} while (hiStart != hiNew);

return ((hiStart << 16) | lo);
Expand All @@ -239,11 +226,11 @@ static inline u32 GXReadMEMReg(u32 addrLo, u32 addrHi)
static inline u32 GXReadCPReg(u32 addrLo, u32 addrHi)
{
u32 hiStart, hiNew, lo;
hiStart = GX_GET_CP_REG(addrHi);
hiStart = __cpReg[addrHi];
do {
hiNew = hiStart;
lo = GX_GET_CP_REG(addrLo);
hiStart = GX_GET_CP_REG(addrHi);
lo = __cpReg[addrLo];
hiStart = __cpReg[addrHi];
} while (hiStart != hiNew);

return ((hiStart << 16) | lo);
Expand All @@ -252,11 +239,11 @@ static inline u32 GXReadCPReg(u32 addrLo, u32 addrHi)
static inline u32 GXReadPEReg(u32 addrLo, u32 addrHi)
{
u32 hiStart, hiNew, lo;
hiStart = GX_GET_PE_REG(addrHi);
hiStart = __peReg[addrHi];
do {
hiNew = hiStart;
lo = GX_GET_PE_REG(addrLo);
hiStart = GX_GET_PE_REG(addrHi);
lo = __peReg[addrLo];
hiStart = __peReg[addrHi];
} while (hiStart != hiNew);

return ((hiStart << 16) | lo);
Expand All @@ -265,11 +252,11 @@ static inline u32 GXReadPEReg(u32 addrLo, u32 addrHi)
static inline u32 GXReadPIReg(u32 addrLo, u32 addrHi)
{
u32 hiStart, hiNew, lo;
hiStart = GX_GET_PI_REG(addrHi);
hiStart = __piReg[addrHi];
do {
hiNew = hiStart;
lo = GX_GET_PI_REG(addrLo);
hiStart = GX_GET_PI_REG(addrHi);
lo = __piReg[addrLo];
hiStart = __piReg[addrHi];
} while (hiStart != hiNew);

return ((hiStart << 16) | lo);
Expand All @@ -279,8 +266,12 @@ static inline u32 GXReadPIReg(u32 addrLo, u32 addrHi)

/////////// OTHER USEFUL DEFINES ///////////
// useful define to check first two GXData members together
// used in GXDisplayList, saves having a union in the struct
#define GX_CHECK_FLUSH() (!(*(u32*)(&gx->vNumNot)))
// used in GXCallDisplayList and GXBegin, saves having a union in the struct
#if OS_BUILD_VERSION >= 20011002L
#define GX_CHECK_FLUSH(gx) ((*(u32*)(&gx->_00))) /* checks both _00 and bpSent */
#else
#define GX_CHECK_FLUSH(gx) (!(*(u32*)(&gx->vNum))) /* checks both vNum and bpSent */
#endif

// do the damn rlwimi thing
#define FAST_FLAG_SET(regOrg, newFlag, shift, size) \
Expand Down
12 changes: 6 additions & 6 deletions include/Dolphin/GX/GXTypes.h
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Original file line number Diff line number Diff line change
Expand Up @@ -110,16 +110,16 @@ typedef struct __GXLightObjPriv {
/////////////// VERTEX INFO ////////////////
// Struct for vertex descriptive info.
typedef struct _GXVtxDescList {
GXAttr mAttr; // _00
GXAttrType mType; // _04
GXAttr attr; // _00
GXAttrType type; // _04
} GXVtxDescList;

// Struct for vertex attribute formats.
typedef struct _GXVtxAttrFmtList {
GXAttr mAttr; // _00
GXCompCnt mCount; // _04
GXCompType mType; // _08
u8 mFrac; // _0C
GXAttr attr; // _00
GXCompCnt count; // _04
GXCompType type; // _08
u8 frac; // _0C
} GXVtxAttrFmtList;

////////////////////////////////////////////
Expand Down
14 changes: 7 additions & 7 deletions include/Dolphin/OS/OSException.h
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Original file line number Diff line number Diff line change
Expand Up @@ -49,19 +49,19 @@ __OSExceptionHandler __OSGetExceptionHandler(__OSException exception);
stw r2, context->gpr[2]; \
stmw r6, context->gpr[6]; \
/* Save GQR1 to GQR7. GQR0 must always be zero */ \
mfspr r0, GQR1; \
mfspr r0, SPR_GQR1; \
stw r0, context->gqr[1]; \
mfspr r0, GQR2; \
mfspr r0, SPR_GQR2; \
stw r0, context->gqr[2]; \
mfspr r0, GQR3; \
mfspr r0, SPR_GQR3; \
stw r0, context->gqr[3]; \
mfspr r0, GQR4; \
mfspr r0, SPR_GQR4; \
stw r0, context->gqr[4]; \
mfspr r0, GQR5; \
mfspr r0, SPR_GQR5; \
stw r0, context->gqr[5]; \
mfspr r0, GQR6; \
mfspr r0, SPR_GQR6; \
stw r0, context->gqr[6]; \
mfspr r0, GQR7; \
mfspr r0, SPR_GQR7; \
stw r0, context->gqr[7];

//////////////////////////////////
Expand Down
8 changes: 4 additions & 4 deletions include/Dolphin/OS/OSFastCast.h
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Original file line number Diff line number Diff line change
Expand Up @@ -35,16 +35,16 @@ static inline void OSInitFastCast(void)
asm {
li r3, OS_GQR_U8
oris r3, r3, OS_GQR_U8
mtspr GQR2, r3
mtspr SPR_GQR2, r3
li r3, OS_GQR_U16
oris r3, r3, OS_GQR_U16
mtspr GQR3, r3
mtspr SPR_GQR3, r3
li r3, OS_GQR_S8
oris r3, r3, OS_GQR_S8
mtspr GQR4, r3
mtspr SPR_GQR4, r3
li r3, OS_GQR_S16
oris r3, r3, OS_GQR_S16
mtspr GQR5, r3
mtspr SPR_GQR5, r3
}
#endif
}
Expand Down
143 changes: 132 additions & 11 deletions include/Dolphin/hw_regs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,90 @@ BEGIN_SCOPE_EXTERN_C
#define HW_REG(reg, type) *(volatile type*)(u32)(reg) // generic HW_REG macro (please do not use this)

/////// HARDWARE REGISTERS ///////

// Command Processor registers.
extern vu16 __CPRegs[51] AT_ADDRESS(0xCC000000);

// offsets for __CPRegs[i]
#define CP_STATUS (0)
#define CP_CONTROL (1)
#define CP_CLEAR (2)
#define CP_PERF_SELECT (3)
#define CP_04 (4)
#define CP_05 (5)
#define CP_06 (6)
#define CP_07 (7)
#define CP_08 (8)
#define CP_09 (9)
#define CP_10 (10)
#define CP_11 (11)
#define CP_12 (12)
#define CP_13 (13)
#define CP_14 (14)
#define CP_15 (15)
#define CP_FIFO_BASE_LO (16)
#define CP_FIFO_BASE_HI (17)
#define CP_FIFO_END_LO (18)
#define CP_FIFO_END_HI (19)
#define CP_FIFO_HI_WATERMARK_LO (20)
#define CP_FIFO_HI_WATERMARK_HI (21)
#define CP_FIFO_LO_WATERMARK_LO (22)
#define CP_FIFO_LO_WATERMARK_HI (23)
#define CP_FIFO_RW_DISTANCE_LO (24)
#define CP_FIFO_RW_DISTANCE_HI (25)
#define CP_FIFO_WRITE_POINTER_LO (26)
#define CP_FIFO_WRITE_POINTER_HI (27)
#define CP_FIFO_READ_POINTER_LO (28)
#define CP_FIFO_READ_POINTER_HI (29)
#define CP_FIFO_BP_LO (30)
#define CP_FIFO_BP_HI (31)
#define CP_XF_RASBUSY_LO (32)
#define CP_XF_RASBUSY_HI (33)
#define CP_XF_CLKS_L0 (34)
#define CP_XF_CLKS_HI (35)
#define CP_XF_WAIT_IN_LO (36)
#define CP_XF_WAIT_IN_HI (37)
#define CP_XF_WAIT_OUT_LO (38)
#define CP_XF_WAIT_OUT_HI (39)
#define CP_VCACHE_METRIC_CHECK_LO (40)
#define CP_VCACHE_METRIC_CHECK_HI (41)
#define CP_VCACHE_METRIC_MISS_LO (42)
#define CP_VCACHE_METRIC_MISS_HI (43)
#define CP_VCACHE_METRIC_STALL_LO (44)
#define CP_VCACHE_METRIC_STALL_HI (45)
#define CP_CLKS_PER_VTX_IN_LO (48)
#define CP_CLKS_PER_VTX_IN_HI (49)
#define CP_CLKS_PER_VTX_OUT (50)

// Pixel Engine registers.
extern vu16 __PERegs[24] AT_ADDRESS(0xCC001000);

// offsets for __PERegs[i]
#define PE_Z_CONFIG (0)
#define PE_ALPHA_CONFIG (1)
#define PE_DEST_ALPHA_CONFIG (2)
#define PE_ALPHA_MODE (3)
#define PE_ALPHA_READ (4)
#define PE_CONTROL_REGISTER (5)
#define PE_06 (6)
#define PE_TOKEN (7)
#define PE_BB_LEFT (8) // bounding box
#define PE_BB_RIGHT (9) // bounding box
#define PE_BB_TOP (10) // bounding box
#define PE_BB_BOTTOM (11) // bounding box
#define PE_PERF_ZCOMP_INPUT_ZCOMPLOC_LO (12)
#define PE_PERF_ZCOMP_INPUT_ZCOMPLOC_HI (13)
#define PE_PERF_ZCOMP_OUTPUT_ZCOMPLOC_LO (14)
#define PE_PERF_ZCOMP_OUTPUT_ZCOMPLOC_HI (15)
#define PE_PERF_ZCOMP_INPUT_LO (16)
#define PE_PERF_ZCOMP_INPUT_HI (17)
#define PE_PERF_ZCOMP_OUTPUT_LO (18)
#define PE_PERF_ZCOMP_OUTPUT_HI (19)
#define PE_PERF_BLEND_INPUT_LO (20)
#define PE_PERF_BLEND_INPUT_HI (21)
#define PE_PERF_EFB_COPY_CLOCKS_LO (22)
#define PE_PERF_EFB_COPY_CLOCKS_HI (23)

// Video Interface registers.
extern vu16 __VIRegs[59] AT_ADDRESS(0xCC002000);

Expand Down Expand Up @@ -77,16 +161,21 @@ extern vu16 __VIRegs[59] AT_ADDRESS(0xCC002000);
#define VI_WIDTH (56)

// Processor Interface registers.
extern vu32 __PIRegs[12] AT_ADDRESS(0xCC003000);
extern vu32 __PIRegs[13] AT_ADDRESS(0xCC003000);

// offsets for __PIRegs[i]
#define PI_INTRPT_SRC (0) // interrupt cause
#define PI_INTRPT_MASK (1) // interrupt mask
#define PI_FIFO_START (3) // FIFO base start
#define PI_FIFO_END (4) // FIFO base end
#define PI_FIFO_PTR (5) // FIFO current write pointer

#define PI_RESETCODE (9) // reset code, used by OSReset
#define PI_FIFO_RESET (6)
#define PI_07 (7)
#define PI_08 (8)
#define PI_RESETCODE (9) // reset code, used by OSReset
#define PI_10 (10)
#define PI_FLIPPER_REV (11)
#define PI_12 (12)

// PI Interrupt causes.
#define PI_INTRPT_ERR (0x1) // GP runtime error
Expand All @@ -109,19 +198,51 @@ extern vu32 __PIRegs[12] AT_ADDRESS(0xCC003000);
extern vu16 __MEMRegs[64] AT_ADDRESS(0xCC004000);

// offsets for __MEMRegs[i]
#define MEM_PROT_1 (0) // protected region 1
#define MEM_PROT_2 (2) // protected region 1
#define MEM_PROT_3 (4) // protected region 1
#define MEM_PROT_4 (6) // protected region 1
#define MEM_PROT_TYPE (8) // protection type

#define MEM_PROT_0_FIRST (0) // protected region 0
#define MEM_PROT_0_LAST (1) // protected region 0
#define MEM_PROT_1_FIRST (2) // protected region 1
#define MEM_PROT_1_LAST (3) // protected region 1
#define MEM_PROT_2_FIRST (4) // protected region 2
#define MEM_PROT_2_LAST (5) // protected region 2
#define MEM_PROT_3_FIRST (6) // protected region 3
#define MEM_PROT_3_LAST (7) // protected region 3
#define MEM_PROT_TYPE (8) // protection type
#define MEM_09 (9)
#define MEM_10 (10)
#define MEM_11 (11)
#define MEM_12 (12)
#define MEM_13 (13)
#define MEM_INTRPT_MASK (14) // interrupt mask
#define MEM_INTRPT_SRC (15) // interrupt cause
#define MEM_INTRPT_FLAG (16) // set when interrupt happens
#define MEM_INTRPT_ADDR_LO (17) // address that caused interrupt
#define MEM_INTRPT_ADDR_HI (18) // address that caused interrupt

#define MEM_UNK_FLAG (20) // unknown memory flag, set in __OSInitMemoryProtection
#define MEM_19 (19)
#define MEM_20 (20) // unknown memory flag, set in __OSInitMemoryProtection
#define MEM_21 (21)
#define MEM_22 (22)
#define MEM_23 (23)
#define MEM_24 (24)
#define MEM_TIMER0_HI (25)
#define MEM_TIMER0_LO (26)
#define MEM_TIMER1_HI (27)
#define MEM_TIMER1_LO (28)
#define MEM_TIMER2_HI (29)
#define MEM_TIMER2_LO (30)
#define MEM_TIMER3_HI (31)
#define MEM_TIMER3_LO (32)
#define MEM_TIMER4_HI (33)
#define MEM_TIMER4_LO (34)
#define MEM_TIMER5_HI (35)
#define MEM_TIMER5_LO (36)
#define MEM_TIMER6_HI (37)
#define MEM_TIMER6_LO (38)
#define MEM_TIMER7_HI (39)
#define MEM_TIMER7_LO (40)
#define MEM_TIMER8_HI (41)
#define MEM_TIMER8_LO (42)
#define MEM_TIMER9_HI (43)
#define MEM_TIMER9_LO (44)

// Digital Signal Processor registers (for audio mixing).
extern vu16 __DSPRegs[32] AT_ADDRESS(0xCC005000);
Expand Down
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