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Look into simplifying data memory

enhancementNew feature or requestNew feature or request

Status: Open.

#27 In physical-computation/Sail-RV32I-common;

· rjlv2 opened on May 22, 2019

JALR might not be compliant with specifications.

Status: Open.

#26 In physical-computation/Sail-RV32I-common;

· rjlv2 opened on May 21, 2019

Possible hazard in combinational logic of control unit

Status: Open.

#25 In physical-computation/Sail-RV32I-common;

· rjlv2 opened on May 21, 2019

Forwarding Unit might not actually require ternary operators.

Status: Open.

#24 In physical-computation/Sail-RV32I-common;

· rjlv2 opened on May 20, 2019

Modified data memory

Status: Open.

#21 In physical-computation/Sail-RV32I-common;

· btsouts opened on May 16, 2019

Code cleanup to meet coding conventions

Status: Open.

#12 In physical-computation/Sail-RV32I-common;

· phillipstanleymarbell opened on Apr 24, 2019

CSR forwarding bug

unconfirmed bug

Status: Open.

#8 In physical-computation/Sail-RV32I-common;

· rjlv2 opened on Mar 10, 2019

Merge RV32_I and narvie's cpu.v

enhancementNew feature or requestNew feature or request

Status: Open.

#2 In physical-computation/Sail-RV32I-common;

· harrysarson opened on Feb 26, 2019

Instruction memory uses LC

Status: Open.

#13 In physical-computation/Sail-RV32I-common;

· harrysarson opened on Jan 29, 2019

Implement a modified Harvard architecture, with separate instruction and data caches but single memory.

Status: Open.

#15 In physical-computation/Sail-RV32I-common;

· rjlv2 opened on Nov 15, 2018

Implement CSR

Status: Open.

#18 In physical-computation/Sail-RV32I-common;

· rjlv2 opened on Oct 12, 2018

Differentiate CSRR instructions from ECALL/EBREAK

Status: Open.

#16 In physical-computation/Sail-RV32I-common;

· rjlv2 opened on Oct 9, 2018