Possible hazard in combinational logic of control unit

[rjlv2]

Specifically ALUSrc control signal. Somehow it accepts (~6).(~4) + (~6).(~5).(4) but not (~6).(~4) + (~6).~(5), though they are the same in boolean logic.

[rjlv2]

This issue seems to be only limited to the branch of Sail used in uncertainty propagation. Works ok on the normal RV32I processor.