modules/zstd: Add support for decoding compressed blocks#1857

Closed

lpawelcz wants to merge 103 commits into

google:mainfrom

antmicro:zstd_compressed_block_dec

Commits on May 16, 2025

modules/zstd/cocotb: Add cocotb testing utilities

koblonczek
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wsipak
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modules/zstd/memory/MemReader: Add cocotb tests

lpawelcz
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wsipak
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modules/zstd/memory/AxiWriter: Add cocotb test

mczyz-antmicro
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wsipak
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modules/zstd/memory/MemWriter: Add cocotb test

lpawelcz
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wsipak
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modules/zstd/memory/README: Describe verilog simulation

lpawelcz
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wsipak
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CI/modules-zstd: Add calls to verilog simulation targets

lpawelcz
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wsipak
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modules/zstd/BUILD: increase pipeline_stages for DecoderMux proc

lpawelcz
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wsipak
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xls/modules/zstd: expose fifo verilog module

lpawelcz
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wsipak
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modules/zstd: Remove MagicNumberDecoder

lpawelcz
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wsipak
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modules/zstd: Remove BlockDecoder proc

lpawelcz
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wsipak
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modules/zstd: Remove DecDemux proc

lpawelcz
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wsipak
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modules/zstd/block_header: Specify new type for the block size

m-torhan
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wsipak
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modules/zstd: Cleanup BlockHeader

lpawelcz
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wsipak
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modules/zstd/BUILD: Introduce common codegen args

lpawelcz
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wsipak
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modules/zstd: Add AxiCsrAccessor

lpawelcz
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wsipak
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modules/zstd: Add CsrConfig

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wsipak
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modules/zstd: Add FrameHeaderDecoder

koblonczek
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wsipak
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modules/zstd: Add BlockHeaderDecoder

m-torhan
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wsipak
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modules/zstd: Add RawBlockDecoder

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wsipak
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modules/zstd: Add RleBlockDecoder

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wsipak
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modules/zstd: Add ZstdDecoder

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wsipak
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modules/zstd/cocotb: Add ZSTD frame generator library

lpawelcz
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wsipak
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dependency_support: Add zstandard python library

lpawelcz
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wsipak
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modules/zstd: Add verilog simulation of the ZstdDecoder

lpawelcz
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wsipak
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modules/zstd: Update documentation

lpawelcz
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wsipak
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modules/zstd: Add AxiRamReader implementation

m-torhan
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wsipak
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modules/zstd/zstd_dec: Add DSLX tests for ZstdDecoder

koblonczek
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wsipak
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modules/zstd/zstd_dec: handle contents of the Status CSR

lpawelcz
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wsipak
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modules/zstd/data_generator: fix formatting

lpawelcz
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wsipak
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modules/zstd/memory:axi_stream_remove_empty: Fix byte ordering

lpawelcz
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wsipak
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modules/zstd/memory/axi_stream_remove_empty: Extract remove_empty_bytes function into a separate proc

lpawelcz
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wsipak
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modules/zstd/memory/axi_writer: Assign parameterized max lane value

lpawelcz
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wsipak
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modules/zstd/memory/mem_writer: Add support for not-full input data packets

lpawelcz
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wsipak
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modules/zstd/memory/mem_writer: Add MemWriterInternal proc

lpawelcz
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wsipak
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modules/zstd/zstd_dec: Write decoded data to the memory

lpawelcz
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wsipak
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modules/zstd/zstd_dec: Remove stream-based output interface

lpawelcz
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wsipak
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modules/zstd/zstd_dec_cocotb_test: Improve Verilog simulation

lpawelcz
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wsipak
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modules/zstd/README: Update output interface description

lpawelcz
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wsipak
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modules/zstd/memory/axi_stream_remove_empty: add fifo module definition for verilog library

lpawelcz
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wsipak
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[TEMP] modules/zstd/memory/mem_writer: Reduce the amount of random test cases

lpawelcz
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wsipak
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modules/zstd/zstd_dec: use regular cast instead of checked_cast on status enums

lpawelcz
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wsipak
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modules/zstd: express data length in bytes

lpawelcz
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wsipak
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modules/zstd: Add buffer implementing desired API

rw1nkler
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wsipak
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modules/zstd: Add FSE procs

rw1nkler
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wsipak
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modules/zstd: Add a proc handling RAM write completion

rw1nkler
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wsipak
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modules/zstd: Add Sequence and Literals Section Header decoders

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wsipak
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modules: Add ShiftBuffer and RefillingShiftBuffer implementation

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wsipak
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modules/zstd: Add FSE tables and lookup decoder

koblonczek
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wsipak
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modules/zstd: Add CommandConstructor proc

RRozak
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wsipak
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modules/zstd: Add Ram demux

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wsipak
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modules/zstd: Add literals decoding

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modules/zstd: Add Huffman literals decoder

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wsipak
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modules/zstd: Add triple output RamDemux

rw1nkler
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wsipak
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Add skeleton of SequenceDecoder

rw1nkler
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wsipak
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modules/zstd: Rework literals decoding to memory-based architecture

lpawelcz
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wsipak
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modules/zstd/BUILD: tag targets as manual

rw1nkler
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wsipak
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modules/zstd: Extend common library

lpawelcz
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wsipak
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modules/zstd: Enable CompressedBlockDecoder

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wsipak
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modules/zstd: Enable CompressedBlockDecoder in ZstdDecoder

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wsipak
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modules/zstd: Add example frame for DSLX tests

rw1nkler
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wsipak
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modules/zstd: Adjust SequenceExecutor

rw1nkler
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wsipak
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modules/zstd: Adjust AxiRam

rw1nkler
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wsipak
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modules/zstd: Add RamMux

rw1nkler
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wsipak
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modules/zstd: Fix HuffmanRawWeightsDecoder

m-torhan
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wsipak
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Fix decoding multiple frames

rw1nkler
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wsipak
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Add support for Compressed FSE tables

koblonczek
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wsipak
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Add test frame for compressed fse tables

rw1nkler
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wsipak
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modules/zstd/zstd_dec: don't use channel arrays for FSE tables access

lpawelcz
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wsipak
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Fix sequence decoding with predefined offset table, add regression test

koblonczek
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wsipak
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Add support for RLE and Repeated fse tables

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wsipak
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Add test frame for repeated and rle tables

rw1nkler
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wsipak
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modules/zstd/BUILD: Add RAM ports rewrite configuration for ZstdDecoder

lpawelcz
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wsipak
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modules/zstd/zstd_dec_wrapper: Remove DSLX native RAM ports

lpawelcz
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wsipak
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modules/zstd: Add RamMerge proc

lpawelcz
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wsipak
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[TEMP] modules/zstd/zstd_dec: Inline HuffmanWeights RamModel

lpawelcz
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wsipak
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[TEMP] modules/zstd/BUILD: Disable ZstdDecoder P&R

lpawelcz
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wsipak
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modules/zstd: Implement HuffmanFseWeightsDecoder

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wsipak
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Count the length of the section with probability frequencies

rw1nkler
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wsipak
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Adjust the design to the changed HuffmanWeightsDecoder

rw1nkler
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wsipak
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Remove duplicate fifo.v file

rw1nkler
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wsipak
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Move test files to a separate directory

rw1nkler
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wsipak
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Move shift_buffer to zstd directory

rw1nkler
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wsipak
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Adjust BUILD files to the recent changes in the toolchain

rw1nkler
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wsipak
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Adjust design to the recent changes in the toolchain

rw1nkler
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wsipak
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BUILD file: fix abseil reference

lpawelcz
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wsipak
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xls/modules/zstd/BUILD: Format with buildifer

lpawelcz
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wsipak
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xls/modules/zstd/memory/BUILD: Format with buildifer

lpawelcz
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wsipak
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modules/zstd: Move verilog sources to rtl subdirectory

lpawelcz
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wsipak
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modules/zstd/memory: Move verilog sources to rtl subdirectory

lpawelcz
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wsipak
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modules/zstd/memory: Add missing module names

lpawelcz
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wsipak
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xls/modules/zstd/external: Add docstring and license for third party sources

lpawelcz
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wsipak
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xls/modules/zstd: Add docstrings to frame generator for DSLX tests

lpawelcz
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wsipak
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modules/zstd/rtl/zstd_dec_wrapper: Add docstring

lpawelcz
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wsipak
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modules/zstd: Rename axi_ram->axi_ram_reader

lpawelcz
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wsipak
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modules/zstd: Remove RESET CSR

lpawelcz
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wsipak
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modules/zstd: fix bazel targets

lpawelcz
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wsipak
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CI/modules-zstd: Remove step for running CC tests

lpawelcz
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wsipak
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modules/zstd: add license
wsipak
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Remove cocotb test of the zstd decoder

rw1nkler
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wsipak
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modules: zstd: formatting and wording changes

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wsipak
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resolve linter errors
wsipak
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use newline before and after headings and lists
wsipak
committed

Commits on May 20, 2025

resolve linter errors
wsipak
committed