riscv: Fix CSR field masking#27
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This PR fixes RISC-V CSR field masking in tlib.
It masks mepc[0] and sepc[0], which are architecturally hardwired to zero, and masks unsupported menvcfg and menvcfgh fields instead of preserving all written bits.
Related to renode/renode#904
Related to renode/renode#905
Related to renode/renode#906