riscv: Fix vector CSR state handling

[whensun]

This PR fixes RISC-V vector CSR state handling in tlib.

It addresses vector CSR masking, mirroring between vcsr, vxrm, and vxsat, vstart masking, and mstatus.VS handling for vector CSR access.

Related to renode/renode#903

[PiotrZierhoffer]

Hi @whensun

Thank you for the contribution.

While we do appreciate the effort to make RISC-V implementation more conformant to the spec, this PR touches too many topics at once.

Can you please split it into smaller chunks, addressing specific issues? Otherwise it will be difficult to review

[whensun]

Thanks for the feedback. That makes sense.

I'll split this into smaller PRs grouped by specific issue areas

[whensun]

I split the original changes into smaller PRs grouped by issue area:

• riscv: Fix vector CSR state handling #26: vector CSR state handling
• riscv: Fix CSR field masking #27: CSR field masking
• riscv: Fix counter access control #28: counter access control
• riscv: Fix privileged trap controls #29: privileged trap controls
• riscv: Fix CSRRW no-read semantics #30: CSRRW no-read semantics
• riscv: Fix LR/SC alignment checks #31: LR/SC alignment checks

Please let me know if this grouping works better for review.