Skip to content

Add Codex-compatible RISC-V operator workflow #2

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
zzwwji-lab wants to merge 1 commit into
base: main
Choose a base branch
from
Open

Add Codex-compatible RISC-V operator workflow #2

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
33 changes: 33 additions & 0 deletions .agents/riscv_operator_workflow/README.md
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,33 @@
# TileLang-RISC-V Operator Workflow

This directory contains the Codex-compatible operator workflow for TileLang-RISCV.

## Entry Points

- `operators.json`: source of truth for initial operator task context
- `validation_report.md`: validation results, SG2044 baseline status, and PR summary draft
- `.agents/tasks/riscv/*.md`: generated Codex task prompts
- `.agents/skills/riscv-operator-workflow/SKILL.md`: Codex workflow instructions
- `docs/get_started/RiscvOperatorAgentWorkflow.md`: user-facing workflow guide

## Generate Tasks

```bash
python maint/scripts/generate_riscv_operator_task.py --list
python maint/scripts/generate_riscv_operator_task.py --all
python maint/scripts/generate_riscv_operator_task.py --operator vector_add
```

## Validate

```bash
bash maint/scripts/run_riscv_operator_workflow_validation.sh
```

The initial workflow validates `vector_add`, `reduce_sum`, and `matmul` through host checks, RISC-V artifact export, and QEMU functional smoke checks.

## SG2044 Boundary

No new SG2044 native run is claimed unless the workflow is actually rerun on SG2044 hardware.

Existing SG2044 baseline data from `docs/get_started/BuildOnSG2044.md` is kept as historical baseline data. QEMU functional smoke checks do not replace SG2044 native RVV validation.
177 changes: 177 additions & 0 deletions .agents/riscv_operator_workflow/operators.json
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,177 @@
{
"workflow_version": 1,
"target": "riscv",
"target_alias": "linalg_riscv",
"validation_note": "The Codex operator workflow can be pre-validated without SG2044 hardware by using x86/arm host execution, RISC-V artifact export, and QEMU. Native SG2044 replay remains the final hardware validation step when SG2044 hardware is available.",
"common_context": {
"riscv_flow": "TileLang -> MLIR Linalg -> MLIR vector/RVV lowering -> LLVM/RISC-V artifact -> host check -> QEMU smoke check -> optional SG2044 native replay",
"sg2044_baseline": [
"Existing documented SG2044 native baseline from docs/get_started/BuildOnSG2044.md:",
"testing/python/riscv/test_riscv_target_parse.py: 2 passed",
"testing/python/riscv/test_riscv_mlir_codegen.py: 33 passed",
"testing/python/riscv/test_riscv_toolchain.py: 3 passed",
"testing/python/riscv/test_riscv_jit_runtime.py: 16 passed",
"This baseline was not rerun during the no-hardware workflow validation pass."
],
"primary_docs": [
".agents/riscv_operator_workflow/README.md",
"docs/get_started/BuildOnSG2044.md",
"docs/get_started/targets.md"
],
"reference_tests": [
"testing/python/riscv/test_riscv_target_parse.py",
"testing/python/riscv/test_riscv_mlir_codegen.py",
"testing/python/riscv/test_riscv_toolchain.py",
"testing/python/riscv/test_riscv_jit_runtime.py",
"testing/python/riscv/test_riscv_examples.py",
"testing/python/riscv/test_riscv_operator_workflow_examples.py",
"testing/python/riscv/test_riscv_qemu_smoke.py"
],
"common_failure_buckets": [
"Generated TileLang/TIR source error",
"Unsupported scheduling or TileLang intrinsic for linalg_riscv",
"MLIR lowering or structured codegen limitation",
"LLVM/RISC-V toolchain setup issue",
"Runtime wrapper, host adapter, QEMU, or optional SG2044 environment issue",
"Test configuration or tolerance mismatch"
]
},
"operators": [
{
"name": "vector_add",
"category": "elementwise",
"task_title": "Implement and validate vector_add for TileLang-RISCV",
"semantics": "For each i in [0, 8), compute C[i] = A[i] + B[i].",
"inputs": [
"A: float32 tensor with shape (8,)",
"B: float32 tensor with shape (8,)"
],
"outputs": [
"C: float32 tensor with shape (8,)"
],
"baseline_reference": [
"PyTorch: lhs + rhs",
"NumPy: lhs + rhs"
],
"baseline_implementation": [
"PyTorch: expected = lhs + rhs",
"NumPy: expected = lhs + rhs"
],
"current_example": "examples/riscv/example_vector_add.py",
"suggested_files": [
"examples/riscv/example_vector_add.py",
"testing/python/riscv/test_riscv_examples.py",
"testing/python/riscv/test_riscv_operator_workflow_examples.py",
"testing/python/riscv/test_riscv_qemu_smoke.py"
],
"schedule_strategy": [
"Use a single serial loop over N.",
"Use a T.block with one spatial axis.",
"Avoid GPU-specific T.Kernel threading, shared memory, warp, or async-copy constructs for this first RISC-V path."
],
"compile_commands": [
"python examples/riscv/example_vector_add.py --emit-mlir --emit-llvm --emit-asm --emit-object --output-dir /tmp/vector_add",
"python examples/riscv/example_vector_add.py --run-host --output-dir /tmp/vector_add",
"python examples/riscv/example_vector_add.py --run-qemu --output-dir /tmp/vector_add"
],
"test_commands": [
"python -m pytest testing/python/riscv/test_riscv_operator_workflow_examples.py -q -k vector_add",
"python -m pytest testing/python/riscv/test_riscv_qemu_smoke.py -q"
],
"success_criteria": [
"Host adapter output matches the PyTorch reference.",
"Artifact export produces one non-empty .s and one non-empty .o file.",
"QEMU smoke emits vector_add.qemu.elf and output matches NumPy reference when a runner is available."
]
},
{
"name": "reduce_sum",
"category": "reduction",
"task_title": "Implement and validate row-wise reduce_sum for TileLang-RISCV",
"semantics": "For each row i in [0, 4), compute B[i] = sum(A[i, k] for k in [0, 8)).",
"inputs": [
"A: float32 tensor with shape (4, 8)"
],
"outputs": [
"B: float32 tensor with shape (4,)"
],
"baseline_reference": [
"PyTorch: data.sum(dim=1)",
"NumPy: data.sum(axis=1)"
],
"baseline_implementation": [
"PyTorch: expected = data.sum(dim=1)",
"NumPy: expected = data.sum(axis=1)"
],
"current_example": "examples/riscv/example_reduce_sum.py",
"suggested_files": [
"examples/riscv/example_reduce_sum.py",
"testing/python/riscv/test_riscv_examples.py",
"testing/python/riscv/test_riscv_operator_workflow_examples.py"
],
"schedule_strategy": [
"Use T.grid(ROWS, COLS) with one spatial row axis and one reduce axis.",
"Use T.init() to zero the output row before accumulation.",
"Keep the first validation shape small and static so qemu artifact generation has fixed memref sizes."
],
"compile_commands": [
"python examples/riscv/example_reduce_sum.py --emit-mlir --emit-llvm --emit-asm --emit-object --output-dir /tmp/reduce_sum",
"python examples/riscv/example_reduce_sum.py --run-host --output-dir /tmp/reduce_sum",
"python examples/riscv/example_reduce_sum.py --run-qemu --output-dir /tmp/reduce_sum"
],
"test_commands": [
"python -m pytest testing/python/riscv/test_riscv_operator_workflow_examples.py -q -k reduce_sum"
],
"success_criteria": [
"Lowered MLIR contains a reduction-friendly structured form such as linalg.reduce or equivalent generic lowering.",
"Host adapter output matches the PyTorch row-sum reference.",
"Artifact export produces one non-empty .s and one non-empty .o file."
]
},
{
"name": "matmul",
"category": "matrix",
"task_title": "Implement and validate small matmul for TileLang-RISCV",
"semantics": "For M=2, N=4, K=3, compute C[i, j] = sum(A[i, k] * B[k, j] for k in [0, 3)).",
"inputs": [
"A: float32 tensor with shape (2, 3)",
"B: float32 tensor with shape (3, 4)"
],
"outputs": [
"C: float32 tensor with shape (2, 4)"
],
"baseline_reference": [
"PyTorch: lhs @ rhs",
"NumPy: lhs @ rhs"
],
"baseline_implementation": [
"PyTorch: expected = lhs @ rhs",
"NumPy: expected = lhs @ rhs"
],
"current_example": "examples/riscv/example_matmul.py",
"suggested_files": [
"examples/riscv/example_matmul.py",
"testing/python/riscv/test_riscv_examples.py",
"testing/python/riscv/test_riscv_operator_workflow_examples.py"
],
"schedule_strategy": [
"Use T.grid(M, N, K) with two spatial axes and one reduce axis.",
"Use T.init() to zero C[i, j] before the K accumulation.",
"Start with plain TIR loops rather than GPU tile intrinsics; move to T.gemm only after the linalg_riscv path supports the needed pattern."
],
"compile_commands": [
"python examples/riscv/example_matmul.py --emit-mlir --emit-llvm --emit-asm --emit-object --output-dir /tmp/matmul",
"python examples/riscv/example_matmul.py --run-host --output-dir /tmp/matmul",
"python examples/riscv/example_matmul.py --run-qemu --output-dir /tmp/matmul"
],
"test_commands": [
"python -m pytest testing/python/riscv/test_riscv_operator_workflow_examples.py -q -k matmul"
],
"success_criteria": [
"Lowered MLIR keeps the matmul semantics visible in structured lowering or produces an equivalent loop form.",
"Host adapter output matches the PyTorch matmul reference.",
"Artifact export produces one non-empty .s and one non-empty .o file."
]
}
]
}
Loading