Add Codex-compatible RISC-V operator workflow

[zzwwji-lab]

Summary

• Add a Codex-compatible TileLang-RISC-V operator workflow catalog, generated tasks, root AGENTS.md, workflow README, repository-local skill, and workflow guide.
• Add three initial validation operators: vector_add, reduce_sum, and matmul.
• Add focused workflow example tests, QEMU smoke coverage, and a catalog-driven validation runner.
• Fix LLVM/MLIR 18 compatibility and default RISC-V hard-float codegen flags needed by the QEMU path.
• Record no-hardware validation results and existing SG2044 baseline data separately.

Validation

python -m pytest testing/python/riscv/test_riscv_operator_workflow.py -q
# 7 passed on Linux/WSL
# 5 passed, 2 skipped on Windows where bash validation is skipped

python -m pytest testing/python/riscv/test_riscv_operator_workflow_examples.py -q
# 6 passed

python -m pytest testing/python/riscv/test_riscv_qemu_smoke.py -q
# 6 passed

python -m pytest testing/python/riscv/test_riscv_examples.py -q
# 6 passed, 26 skipped

bash maint/scripts/run_riscv_operator_workflow_validation.sh
# 85 passed, 26 skipped
# vector_add host check passed
# vector_add qemu check passed
# reduce_sum host check passed
# reduce_sum qemu check passed
# matmul host check passed
# matmul qemu check passed

SG2044 Status

No new SG2044 native run was performed because SG2044 hardware was not available.

Existing SG2044 baseline data from docs/get_started/BuildOnSG2044.md is included as historical baseline data. The current validation covers host checks, RISC-V artifact export, and QEMU functional smoke checks. It does not replace SG2044 native RVV validation.

Notes

testing/python/riscv/test_riscv_examples.py preserves the original 16-entry RISC-V example list from upstream. The current upstream repository does not contain all corresponding examples/riscv/ scripts yet, so missing legacy example filenames are skipped rather than removed from the coverage entry point.

Addresses #1.

[zhanghb97]

Thanks for the PR. I think the overall direction looks good.

A few suggestions from my side:

• I can help provide access to the RVV server SG2044. I would suggest validating this workflow directly on real hardware instead of relying on QEMU.
• After running on SG2044, please check whether the current compilation options modification is still appropriate, for example, rv64gc may not be suitable for the real hardware/RVV path.
• For future work, please also think about how this workflow can support a large number of operator generations. This does not need to be addressed in this PR, but it would be good to evaluate whether the current process for adding a new operator can scale to batch onboarding of operators.