增加 A210 芯片支持

Documentation/devicetree/bindings/clock/zhihe,a210-ccu.yaml

@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/zhihe,a210-ccu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Zhihe A210 Clock Control Unit (CCU)
+
+maintainers:
+  - Zhiguo Zhu <zhiguo.zhu@linux.alibaba.com>
+
+description:
+  The CCU (Clock Control Unit) is a hardware-level automatic clock
+  management block embedded in each power domain of the Zhihe A210 SoC.
+  Unlike the main clock controller (zhihe,a210-clk) which provides PLL,
+  divider, gate and mux operations driven by software, the CCU
+  autonomously sequences clock gating or scaling delays when its parent
+  power domain transitions between power states. It does not expose
+  clock outputs to consumers and is not required for basic SoC
+  operation; the system functions correctly without CCU nodes present.
+
+properties:
+  compatible:
+    const: zhihe,a210-ccu
+
+  reg:
+    minItems: 1
+    maxItems: 8
+
+  zhihe,ccu-mode:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+    description:
+      CCU operating mode. 0 (default) selects gating mode where clocks
+      are simply gated/ungated during power transitions. 1 selects
+      scaling mode where clock frequencies are ramped gradually.
+      Most power domains use gating mode; this property can be omitted
+      in that case.
+
+  zhihe,ccu-dly-time:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: Per-CCU delay time value.
+
+  zhihe,ccu-dly-time-step:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: Per-CCU delay time step value.
+
+  zhihe,ccu-ratio:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: Per-CCU divider ratio (scaling mode only).
+
+required:
+  - compatible
+  - reg
+  - zhihe,ccu-dly-time
+  - zhihe,ccu-dly-time-step
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@5910000 {
+        compatible = "zhihe,a210-ccu";
+        reg = <0x05910000 0x2c>, <0x05920000 0x2c>;
+        zhihe,ccu-dly-time = <0x5e 0x5e>;
+        zhihe,ccu-dly-time-step = <0x3 0x3>;
+    };

Documentation/devicetree/bindings/clock/zhihe,a210-clk.yaml

@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/zhihe,a210-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Zhihe A210 Clock Controller
+
+maintainers:
+  - Zhiguo Zhu <zhiguo.zhu@linux.alibaba.com>
+
+description:
+  The Zhihe A210 SoC contains several clock controllers spread across
+  different subsystems (top, peri, gpu, pcie, usb, vi, vp, vo, npu, d2d).
+  Each controller manages PLLs, dividers, gates and muxes for its
+  subsystem. The register regions consumed by a controller depend on the
+  specific compatible string.
+
+properties:
+  compatible:
+    enum:
+      - zhihe,a210-clk
+      - zhihe,a210-peri-clk
+      - zhihe,a210-gpu-clk
+      - zhihe,a210-pcie-clk
+      - zhihe,a210-usb-clk
+      - zhihe,a210-vi-clk
+      - zhihe,a210-vp-clk
+      - zhihe,a210-vo-clk
+      - zhihe,a210-npu-clk
+      - zhihe,a210-clk-emu
+      - zhihe,a210-clk-haps
+
+  reg:
+    minItems: 1
+    maxItems: 9
+
+  reg-names:
+    minItems: 1
+    maxItems: 9
+
+  clocks:
+    description: Input reference oscillators.
+    minItems: 1
+    maxItems: 3
+
+  clock-names:
+    minItems: 1
+    maxItems: 3
+    items:
+      enum:
+        - osc-32k
+        - osc-24m
+        - rc-24m
+
+  "#clock-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@260000 {
+        compatible = "zhihe,a210-clk";
+        reg = <0x00260000 0x1000>;
+        reg-names = "pll-wrap";
+        clocks = <&osc_32k>, <&osc_24m>, <&rc_24m>;
+        clock-names = "osc-32k", "osc-24m", "rc-24m";
+        #clock-cells = <1>;
+    };

Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml

@@ -21,6 +21,7 @@ properties:
       - snps,axi-dma-1.01a
       - intel,kmb-axi-dma
       - starfive,jh7110-axi-dma
+      - zhihe,a210-axi-dma
 
   reg:
     minItems: 1

Documentation/devicetree/bindings/firmware/zhihe,a210-aon.yaml

@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/zhihe,a210-aon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Zhihe A210 AON (Always-On) Subsystem Firmware
+
+maintainers:
+  - Zhiguo Zhu <zhiguo.zhu@linux.alibaba.com>
+
+description:
+  The Always-On (AON) subsystem of the Zhihe A210 SoC runs a dedicated
+  firmware and communicates with the application processor over a
+  mailbox. This node describes the AON control registers, its firmware
+  image and the mailbox channel used to reach it.
+
+properties:
+  compatible:
+    const: zhihe,a210-aon
+
+  reg:
+    minItems: 3
+    maxItems: 3
+
+  reg-names:
+    minItems: 3
+    maxItems: 3
+    items:
+      enum:
+        - aon-base
+        - aon-reset
+        - aon-sync
+
+  firmware-name:
+    maxItems: 1
+    description: Name of the AON firmware image to load.
+
+  mboxes:
+    maxItems: 1
+
+  mbox-names:
+    items:
+      - const: aon0
+
+  zhihe,protocol-version:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: AON protocol version.
+
+  "#mbox-cells":
+    const: 2
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - mboxes
+
+additionalProperties: false
+
+examples:
+  - |
+    aon {
+        compatible = "zhihe,a210-aon";
+        reg = <0x308f8000 0x10000>,
+              <0x30842018 0x4>,
+              <0x30846144 0x4>;
+        reg-names = "aon-base", "aon-reset", "aon-sync";
+        firmware-name = "a210-aon.bin";
+        mboxes = <&mbox_920 1 0>;
+        mbox-names = "aon0";
+        #mbox-cells = <2>;
+        zhihe,protocol-version = <1>;
+    };

Documentation/devicetree/bindings/mailbox/zhihe,a210-mailbox.yaml

@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/zhihe,a210-mailbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Zhihe A210 Mailbox Controller
+
+maintainers:
+  - Zhiguo Zhu <zhiguo.zhu@linux.alibaba.com>
+
+description:
+  Mailbox controller for the Zhihe A210 SoC providing inter-processor
+  communication channels between the application processor and other
+  cores such as the AON (Always-On) subsystem.
+
+properties:
+  compatible:
+    enum:
+      - zhihe,a210-mailbox
+      - zhihe,a210-mailbox-v2
+
+  reg:
+    minItems: 1
+    maxItems: 8
+
+  reg-names:
+    minItems: 1
+    maxItems: 8
+    items:
+      enum:
+        - interrupt
+        - local0
+        - local1
+        - remote0
+        - remote1
+        - remote2
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  resets:
+    minItems: 1
+    maxItems: 2
+
+  interrupts:
+    maxItems: 1
+
+  zhihe,icu-cpu-id:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Local ICU CPU index for this mailbox instance.
+
+  "#mbox-cells":
+    const: 2
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - "#mbox-cells"
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          const: zhihe,a210-mailbox-v2
+    then:
+      properties:
+        reg:
+          minItems: 3
+        reg-names:
+          minItems: 3
+    else:
+      properties:
+        reg:
+          minItems: 4
+        reg-names:
+          minItems: 4
+
+additionalProperties: false
+
+examples:
+  - |
+    mailbox@321000 {
+        compatible = "zhihe,a210-mailbox-v2";
+        reg = <0x00321000 0x1000>,
+              <0x00320000 0x1000>,
+              <0x00311000 0x1000>;
+        reg-names = "interrupt", "local0", "remote0";
+        clocks = <&clk_peri 0>, <&clk_peri 1>;
+        resets = <&rst 0>, <&rst 1>;
+        interrupt-parent = <&intc>;
+        interrupts = <336>;
+        zhihe,icu-cpu-id = <0>;
+        #mbox-cells = <2>;
+    };

Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml

@@ -20,6 +20,7 @@ properties:
       - rockchip,rk3588-dwcmshc
       - snps,dwcmshc-sdhci
       - thead,th1520-dwcmshc
+      - zhihe,a210-dwcmshc
 
   reg:
     maxItems: 1