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Performance optimization of SM4-XTS encryption and decryption on RISC-V #6

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Performance optimization of SM4-XTS encryption and decryption on RISC-V #6

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14 changes: 14 additions & 0 deletions .github/workflows/riscv-more-cross-compiles.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -149,6 +149,7 @@ jobs:
# crypto/chacha/chacha_riscv.c (with ZVKB)
# crypto/modes/gcm128.c (with ZVKG/ZVKB)
# crypto/sm3/asm/sm3-riscv64-zvksh.pl
# crypto/sm4/asm/sm4-riscv64-zvbb-zvkg-zvksed.pl
# crypto/sm4/asm/sm4-riscv64-zvksed.pl
# crypto/aes/asm/aes-riscv64-zvbb-zvkg-zvkned.pl
# crypto/aes/asm/aes-riscv64-zvkb-zvkned.pl
Expand All @@ -164,6 +165,19 @@ jobs:
qemucpu: "rv64,zba=true,zbb=true,zbc=true,zbs=true,zbkb=true,zbkc=true,zbkx=true,zknd=true,zkne=true,zknh=true,zksed=true,zksh=true,zkr=true,zkt=true,v=true,vlen=128,zvbb=true,zvbc=true,zvkb=true,zvkg=true,zvkned=true,zvknha=true,zvknhb=true,zvksed=true,zvksh=true",
opensslcapsname: riscvcap, # OPENSSL_riscvcap
opensslcaps: "rv64gc_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_zkr_zkt_v_zvbb_zvbc_zvkb_zvkg_zvkned_zvknha_zvknhb_zvksed_zvksh"
}, {
# RV64GC with ZVKB and ZVKSED
# crypto/sm4/asm/sm4-riscv64-zvksed.pl
arch: riscv64-linux-gnu,
libs: libc6-dev-riscv64-cross,
target: linux64-riscv64,
fips: no,
# do not use zvkb flag for qemucpu as ubuntu-latest (24.04) uses QEMU 8.2.2
# see https://lists.nongnu.org/archive/html/qemu-devel/2024-05/msg02231.html
# Should be zvkb=true,zvksed=true
qemucpu: "rv64,v=true,vlen=128,zvbb=true,zvksed=true",
opensslcapsname: riscvcap, # OPENSSL_riscvcap
opensslcaps: "rv64gc_zvkb_zvksed"
}, {
# RV64GC with all currently OpenSSL-supported extensions, with zvl256
# crypto/sha/asm/sha512-riscv64-zvkb-zvknhb.pl
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20 changes: 20 additions & 0 deletions crypto/perlasm/riscv.pm
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Expand Up @@ -488,6 +488,17 @@ sub vadd_vx {
return ".word ".($template | ($vm << 25) | ($vs2 << 20) | ($rs1 << 15) | ($vd << 7));
}

sub vand_vi {
# vand.vi vd, vs2, uimm
my $template = 0b0_010011_00000_00000_011_00000_1010111;
my $vd = read_vreg shift; # vd (vN) -> [7:11]
my $vs2 = read_vreg shift; # vs2 (vN) -> [20:24]
my $uimm = shift; # uimm (imm5) -> [15:19]
my $uimm_i4_0 = $uimm & 0b11111;

return ".word ".($template | ($vs2 << 20) | ($uimm_i4_0 << 15) | ($vd << 7));
}

sub vsub_vv {
# vsub.vv vd, vs2, vs1, vm
my $template = 0b000010_0_00000_00000_000_00000_1010111;
Expand Down Expand Up @@ -1129,4 +1140,13 @@ sub vrgather_vv{
return ".word ".($template | ($vs2 << 20) | ($vs1 << 15 ) | ($vd << 7));
}

sub vrgatherei16_vv{
# vrgatherei16.vv vd, vs2, vs1
my $template = 0b0011101_00000_00000_000_00000_1010111;
my $vd = read_vreg shift;
my $vs2 = read_vreg shift;
my $vs1 = read_vreg shift;
return ".word ".($template | ($vs2 << 20) | ($vs1 << 15 ) | ($vd << 7));
}

1;
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