Optimization of small-packet decryption performance for AES-128-XTS on RISC-V#5
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Optimization of small-packet decryption performance for AES-128-XTS on RISC-V#5zl523856 wants to merge 1 commit into
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…n RISC-V Original code employed m4 vector configuration for decrypting packets of varying sizes, which caused performance degradation for 16-byte packets. The optimized version adopted m2 configuration with a 2-block loop to enhance small packet decryption performance. Hardware simulation environment verification data: Decrypt Test Baseline Optimized Improvement ratio 16 bytes 10108.77k 11266.69k 11% 64 bytes 15911.04k 16081.97k 1% Test Verification All relevant tests pass in the default build configuration: make test All tests successful. Files=350, Tests=4030, 8205 wallclock secs (94.74 usr 28.15 sys + 5844.99 cusr 2052.35 csys = 8020.23 CPU) Result: PASS
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Original code employed m4 vector configuration for decrypting packets of varying sizes, which caused performance degradation for 16-byte packets. The optimized version adopted m2 configuration with a 2-block loop to enhance small packet decryption performance.
Hardware simulation environment verification data:
Decrypt Test Baseline Optimized Improvement ratio
16 bytes 10108.77k 11266.69k 11%
64 bytes 15911.04k 16081.97k 1%
Test Verification
All relevant tests pass in the default build configuration: make test All tests successful. Files=350, Tests=4030, 8205 wallclock secs (94.74 usr 28.15 sys + 5844.99 cusr 2052.35 csys = 8020.23 CPU) Result: PASS
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