riscv64: add disassembler support for Zabha

riscv64/riscv64asm/objdump_test.go

@@ -88,6 +88,12 @@ func allowedMismatchObjdump(text string, inst *Inst, dec ExtInst, version string
 		return true
 	}
 
+	// Zabha instructions (amocas.b/h) require both zabha and zacas
+	// in the ELF attributes, supported by objdump 2.43 and later.
+	if strings.HasPrefix(dec.text, ".insn") && isZabhaOp(inst.Op) && !objdumpVersionAtLeast(version, "2.43") {
+		return true
+	}
+
 	return false
 }
 
@@ -128,3 +134,11 @@ func isZvkOp(op Op) bool {
 	}
 	return false
 }
+
+func isZabhaOp(op Op) bool {
+	// All Zabha instructions are AMO* byte (.B) or halfword (.H) operations,
+	// including .AQ/.RL/.AQRL variants (e.g. AMOADD.B.AQ contains ".B").
+	name := opstr[op]
+	return (strings.Contains(name, ".B") || strings.Contains(name, ".H")) &&
+		strings.HasPrefix(name, "AMO")
+}

riscv64/riscv64asm/objdumpext_test.go

@@ -289,7 +289,7 @@ func writeELF64(f *os.File, size int) error {
 	strtabsize := len("\x00.text\x00.riscv.attributes\x00.shstrtab\x00")
 	// RISC-V objdump needs the .riscv.attributes section to identify extensions.
 	exts := "rv64i2p0_m2p0_a2p0_f2p0_d2p0_q2p0_c2p0_v1p0_" +
-		"zicbom1p0_zicbop1p0_zicboz1p0_zicond1p0_zmmul1p0_" +
+		"zabha1p0_zacas1p0_zicbom1p0_zicbop1p0_zicboz1p0_zicond1p0_zmmul1p0_" +
 		"zfh1p0_zfhmin1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_" +
 		"zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0"
 	b := buildRISCVAttributes(exts)

riscv64/riscv64asm/plan9x.go

@@ -58,8 +58,21 @@ goSyntaxSwitch:
 		AMOOR_D_RL, AMOOR_D_AQRL, AMOOR_W, AMOOR_W_AQ, AMOOR_W_RL, AMOOR_W_AQRL, AMOSWAP_D,
 		AMOSWAP_D_AQ, AMOSWAP_D_RL, AMOSWAP_D_AQRL, AMOSWAP_W, AMOSWAP_W_AQ, AMOSWAP_W_RL,
 		AMOSWAP_W_AQRL, AMOXOR_D, AMOXOR_D_AQ, AMOXOR_D_RL, AMOXOR_D_AQRL, AMOXOR_W,
-		AMOXOR_W_AQ, AMOXOR_W_RL, AMOXOR_W_AQRL, SC_D, SC_D_AQ, SC_D_RL, SC_D_AQRL,
-		SC_W, SC_W_AQ, SC_W_RL, SC_W_AQRL:
+		AMOXOR_W_AQ, AMOXOR_W_RL, AMOXOR_W_AQRL, AMOADD_B, AMOADD_B_AQ, AMOADD_B_AQRL,
+		AMOADD_B_RL, AMOADD_H, AMOADD_H_AQ, AMOADD_H_AQRL, AMOADD_H_RL, AMOAND_B,
+		AMOAND_B_AQ, AMOAND_B_AQRL, AMOAND_B_RL, AMOAND_H, AMOAND_H_AQ, AMOAND_H_AQRL,
+		AMOAND_H_RL, AMOCAS_B, AMOCAS_B_AQ, AMOCAS_B_AQRL, AMOCAS_B_RL, AMOCAS_H,
+		AMOCAS_H_AQ, AMOCAS_H_AQRL, AMOCAS_H_RL, AMOMAXU_B, AMOMAXU_B_AQ, AMOMAXU_B_AQRL,
+		AMOMAXU_B_RL, AMOMAXU_H, AMOMAXU_H_AQ, AMOMAXU_H_AQRL, AMOMAXU_H_RL, AMOMAX_B,
+		AMOMAX_B_AQ, AMOMAX_B_AQRL, AMOMAX_B_RL, AMOMAX_H, AMOMAX_H_AQ, AMOMAX_H_AQRL,
+		AMOMAX_H_RL, AMOMINU_B, AMOMINU_B_AQ, AMOMINU_B_AQRL, AMOMINU_B_RL, AMOMINU_H,
+		AMOMINU_H_AQ, AMOMINU_H_AQRL, AMOMINU_H_RL, AMOMIN_B, AMOMIN_B_AQ, AMOMIN_B_AQRL,
+		AMOMIN_B_RL, AMOMIN_H, AMOMIN_H_AQ, AMOMIN_H_AQRL, AMOMIN_H_RL, AMOOR_B,
+		AMOOR_B_AQ, AMOOR_B_AQRL, AMOOR_B_RL, AMOOR_H, AMOOR_H_AQ, AMOOR_H_AQRL,
+		AMOOR_H_RL, AMOSWAP_B, AMOSWAP_B_AQ, AMOSWAP_B_AQRL, AMOSWAP_B_RL, AMOSWAP_H,
+		AMOSWAP_H_AQ, AMOSWAP_H_AQRL, AMOSWAP_H_RL, AMOXOR_B, AMOXOR_B_AQ, AMOXOR_B_AQRL,
+		AMOXOR_B_RL, AMOXOR_H, AMOXOR_H_AQ, AMOXOR_H_AQRL, AMOXOR_H_RL,
+		SC_D, SC_D_AQ, SC_D_RL, SC_D_AQRL, SC_W, SC_W_AQ, SC_W_RL, SC_W_AQRL:
 		// Atomic instructions have special operand order.
 		args[2], args[1] = args[1], args[2]