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riscv64: add disassembler support for Zcb #17

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efa860c
riscv64: add disassembler support for Zcb
Jul 16, 2026
4e83678
remove the blank line
Jul 16, 2026
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3 changes: 3 additions & 0 deletions riscv64/riscv64asm/arg.go
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Original file line number Diff line number Diff line change
Expand Up @@ -140,4 +140,7 @@ const (
arg_c_nzuimm10
arg_c_imm12
arg_c_nzimm18

arg_c_uimm1
arg_c_uimm2
)
72 changes: 72 additions & 0 deletions riscv64/riscv64asm/decode.go
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Original file line number Diff line number Diff line change
Expand Up @@ -372,6 +372,14 @@ func decodeArg(aop argType, x uint32, index int) Arg {
}
return Simm{int32(imm), true, 18}

case arg_c_uimm2:
imm := ((x>>6)&1) | (((x>>5)&1) << 1)
return Uimm{imm, false}

case arg_c_uimm1:
imm := ((x >> 5) & 0x1) << 1
return Uimm{imm, false}

default:
return nil
}
Expand Down Expand Up @@ -591,6 +599,70 @@ func convertCompressedIns(f *instFormat, args Args) Args {
newargs[0] = Reg(X0)
newargs[1] = CSR(CYCLE)
newargs[2] = Reg(X0)

case C_LBU:
f.op = LBU
newargs[0] = args[0]
newargs[1] = RegOffset{args[1].(Reg), Simm{int32(args[2].(Uimm).Imm), true, 12}}

case C_LHU:
f.op = LHU
newargs[0] = args[0]
newargs[1] = RegOffset{args[1].(Reg), Simm{int32(args[2].(Uimm).Imm), true, 12}}

case C_LH:
f.op = LH
newargs[0] = args[0]
newargs[1] = RegOffset{args[1].(Reg), Simm{int32(args[2].(Uimm).Imm), true, 12}}

case C_SB:
f.op = SB
newargs[0] = args[0]
newargs[1] = RegOffset{args[1].(Reg), Simm{int32(args[2].(Uimm).Imm), true, 12}}

case C_SH:
f.op = SH
newargs[0] = args[0]
newargs[1] = RegOffset{args[1].(Reg), Simm{int32(args[2].(Uimm).Imm), true, 12}}

case C_MUL:
f.op = MUL
newargs[0] = args[0]
newargs[1] = args[0]
newargs[2] = args[1]

case C_NOT:
f.op = XORI
newargs[0] = args[0]
newargs[1] = args[0]
newargs[2] = Simm{-1, true, 12}

case C_SEXT_B:
f.op = SEXT_B
newargs[0] = args[0]
newargs[1] = args[0]

case C_SEXT_H:
f.op = SEXT_H
newargs[0] = args[0]
newargs[1] = args[0]

case C_ZEXT_B:
f.op = ANDI
newargs[0] = args[0]
newargs[1] = args[0]
newargs[2] = Simm{255, true, 12}

case C_ZEXT_H:
f.op = ZEXT_H
newargs[0] = args[0]
newargs[1] = args[0]

case C_ZEXT_W:
f.op = ADD_UW
newargs[0] = args[0]
newargs[1] = args[0]
newargs[2] = Reg(X0)
}
return newargs
}
2 changes: 1 addition & 1 deletion riscv64/riscv64asm/objdumpext_test.go
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Original file line number Diff line number Diff line change
Expand Up @@ -290,7 +290,7 @@ func writeELF64(f *os.File, size int) error {
// RISC-V objdump needs the .riscv.attributes section to identify extensions.
exts := "rv64i2p0_m2p0_a2p0_f2p0_d2p0_q2p0_c2p0_v1p0_" +
"zicbom1p0_zicbop1p0_zicboz1p0_zicond1p0_zmmul1p0_" +
"zfh1p0_zfhmin1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_" +
"zfh1p0_zfhmin1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_zcb1p0_" +
"zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0"
b := buildRISCVAttributes(exts)
sect = elf.Section64{
Expand Down
3 changes: 2 additions & 1 deletion riscv64/riscv64asm/plan9x.go
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Original file line number Diff line number Diff line change
Expand Up @@ -71,7 +71,7 @@ goSyntaxSwitch:

case ADDIW:
if inst.Args[2].(Simm).Imm == 0 {
op = "MOVW"
op = "SEXTW"
args = args[:len(args)-1]
}

Expand Down Expand Up @@ -390,6 +390,7 @@ goSyntaxSwitch:

case VSETVL:
args[0], args[2] = args[2], args[0]

}

// Reverse args, placing dest last.
Expand Down
48 changes: 48 additions & 0 deletions riscv64/riscv64asm/tables.go
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17 changes: 17 additions & 0 deletions riscv64/riscv64asm/testdata/gnucases.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -425,6 +425,23 @@ b373530e| czero.nez x7,x6,x5
13e0321c| prefetch.w 448(x5)
13e07200| ori x0,x5,7

# "Zc*" Extension for Code Size Reduction, Version 1.0.0

# 27.8: "zcb" Extension
6c81| lbu x11,3(x10)
2c85| lhu x11,2(x10)
6c85| lh x11,2(x10)
2c89| sb x11,2(x10)
2c8d| sh x11,2(x10)
619d| zext.b x10,x10
659d| sext.b x10,x10
699d| zext.h x10,x10
6d9d| sext.h x10,x10
759d| not x10,x10
4d9d| mul x10,x10,x11
719d| zext.w x10,x10
0125| sext.w x10,x10

# "B" Extension for Bit Manipulation, Version 1.0.0

# 28.4.1. Zba: Address generation
Expand Down
21 changes: 19 additions & 2 deletions riscv64/riscv64asm/testdata/plan9cases.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,8 @@ b3027300| ADD X7, X6, X5
93870900| MOV X19, X15
93070100| MOV X2, X15
9b02f37f| ADDIW $2047, X6, X5
1b830a00| MOVW X21, X6
1b810a00| MOVW X21, X2
1b830a00| SEXTW X21, X6
1b810a00| SEXTW X21, X2
bb027300| ADDW X7, X6, X5
afb26300| AMOADDD X6, (X7), X5
afb26304| AMOADDD X6, (X7), X5
Expand Down Expand Up @@ -378,6 +378,23 @@ b373530e| CZERONEZ X5, X6, X7
13e0321c| PREFETCHW 448(X5)
13e07200| ORI $7, X5, X0

# "Zc*" Extension for Code Size Reduction, Version 1.0.0

# 27.8: "zcb" Extension
6c81| MOVBU 3(X10), X11
2c85| MOVHU 2(X10), X11
6c85| MOVH 2(X10), X11
2c89| MOVB X11, 2(X10)
2c8d| MOVH X11, 2(X10)
619d| MOVBU X10, X10
659d| SEXTB X10, X10
699d| ZEXTH X10, X10
6d9d| SEXTH X10, X10
759d| NOT X10, X10
4d9d| MUL X11, X10, X10
719d| ZEXTW X10, X10
0125| SEXTW X10, X10

# "B" Extension for Bit Manipulation, Version 1.0.0

# 28.4.1. Zba: Address generation
Expand Down
8 changes: 8 additions & 0 deletions riscv64/riscv64spec/spec.go
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Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,7 @@ var extensions = []string{
"rv_zbb",
"rv_zbc",
"rv_zbs",
"rv_zcb",
"rv_zicbo",
"rv_zfh",
"rv_zfhmin",
Expand All @@ -57,6 +58,7 @@ var extensions = []string{
"rv64_zba",
"rv64_zbb",
"rv64_zbs",
"rv64_zcb",
"rv64_zfh",
}

Expand Down Expand Up @@ -507,6 +509,12 @@ func decodeArgs(arg string, op string) string {

case arg == "c_nzimm18lo":
return "arg_c_nzimm18"

case arg == "c_uimm2":
return "arg_c_uimm2"

case arg == "c_uimm1":
return "arg_c_uimm1"
}
return ""
}
Expand Down
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