riscv64: add disassembler support for Zvbb and Zvbc

riscv64/riscv64asm/arg.go

@@ -105,6 +105,7 @@ const (
 	arg_vtype_zimm10
 	arg_vtype_zimm11
 	arg_bimm12
+	arg_zimm6
 	arg_imm20
 	arg_jimm20
 	arg_shamt5

riscv64/riscv64asm/decode.go

@@ -236,6 +236,11 @@ func decodeArg(aop argType, x uint32, index int) Arg {
 		imm := x << 12 >> 27
 		return Uimm{imm, true}
 
+	case arg_zimm6:
+		// 6-bit unsigned immediate from bit 26 (hi) and bits 19:15 (lo)
+		imm := (x >> 15) & 0x1f | (x >> 21) & 0x20
+		return Uimm{imm, true}
+
 	case arg_vtype_zimm10:
 		imm := x << 2 >> 22
 		return VType(imm)

riscv64/riscv64asm/objdumpext_test.go

@@ -291,7 +291,7 @@ func writeELF64(f *os.File, size int) error {
 	exts := "rv64i2p0_m2p0_a2p0_f2p0_d2p0_q2p0_c2p0_v1p0_" +
 		"zicbom1p0_zicbop1p0_zicboz1p0_zicond1p0_zmmul1p0_" +
 		"zfh1p0_zfhmin1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_" +
-		"zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0"
+		"zvbb1p0_zvbc1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0"
 	b := buildRISCVAttributes(exts)
 	sect = elf.Section64{
 		Name:      uint32(len("\x00.text\x00")),

riscv64/riscv64asm/testdata/gnucases.txt

@@ -1781,6 +1781,50 @@ d730209e|	vmv1r.v v1,v2
 57b2819e|	vmv4r.v v4,v8
 57b0839e|	vmv8r.v v0,v8
 
+# 33.2.1. Zvbb - Vector Basic Bit-manipulation
+d7812006|	vandn.vv v3,v2,v1
+d7812004|	vandn.vv v3,v2,v1,v0.t
+d7412506|	vandn.vx v3,v2,x10
+d7412504|	vandn.vx v3,v2,x10,v0.t
+d721254a|	vbrev.v v3,v2
+d7212548|	vbrev.v v3,v2,v0.t
+d721244a|	vbrev8.v v3,v2
+d7212448|	vbrev8.v v3,v2,v0.t
+d7a1244a|	vrev8.v v3,v2
+d7a12448|	vrev8.v v3,v2,v0.t
+d721264a|	vclz.v v3,v2
+d7212648|	vclz.v v3,v2,v0.t
+d7a1264a|	vctz.v v3,v2
+d7a12648|	vctz.v v3,v2,v0.t
+d721274a|	vcpop.v v3,v2
+d7212748|	vcpop.v v3,v2,v0.t
+d78120d6|	vwsll.vv v3,v2,v1
+d78120d4|	vwsll.vv v3,v2,v1,v0.t
+d74125d6|	vwsll.vx v3,v2,x10
+d74125d4|	vwsll.vx v3,v2,x10,v0.t
+d7b127d6|	vwsll.vi v3,v2,15
+d7b127d4|	vwsll.vi v3,v2,15,v0.t
+d7812056|	vrol.vv v3,v2,v1
+d7812054|	vrol.vv v3,v2,v1,v0.t
+d7412556|	vrol.vx v3,v2,x10
+d7412554|	vrol.vx v3,v2,x10,v0.t
+d7b12752|	vror.vi v3,v2,15
+d7b12750|	vror.vi v3,v2,15,v0.t
+d7812052|	vror.vv v3,v2,v1
+d7812050|	vror.vv v3,v2,v1,v0.t
+d7412552|	vror.vx v3,v2,x10
+d7412550|	vror.vx v3,v2,x10,v0.t
+
+# 33.2.2. Zvbc - Vector Carryless Multiplication
+d7a12032|	vclmul.vv v3,v2,v1
+d7a12030|	vclmul.vv v3,v2,v1,v0.t
+d7612532|	vclmul.vx v3,v2,x10
+d7612530|	vclmul.vx v3,v2,x10,v0.t
+d7a12036|	vclmulh.vv v3,v2,v1
+d7a12034|	vclmulh.vv v3,v2,v1,v0.t
+d7612536|	vclmulh.vx v3,v2,x10
+d7612534|	vclmulh.vx v3,v2,x10,v0.t
+
 # 32.2.4: Vector GCM/GMAC
 f7a120b2|	vghsh.vv v3,v2,v1
 f7a128a2|	vgmul.vv v3,v2

riscv64/riscv64asm/testdata/plan9cases.txt

@@ -1737,6 +1737,50 @@ d730209e|	VMV1RV V2, V1
 
 # Zvk: Vector Cryptography Extensions
 
+# 33.2.1. Zvbb - Vector Basic Bit-manipulation
+d7812006|	VANDNVV V1, V2, V3
+d7812004|	VANDNVV V1, V2, V0, V3
+d7412506|	VANDNVX X10, V2, V3
+d7412504|	VANDNVX X10, V2, V0, V3
+d721254a|	VBREVV V2, V3
+d7212548|	VBREVV V2, V0, V3
+d721244a|	VBREV8V V2, V3
+d7212448|	VBREV8V V2, V0, V3
+d7a1244a|	VREV8V V2, V3
+d7a12448|	VREV8V V2, V0, V3
+d721264a|	VCLZV V2, V3
+d7212648|	VCLZV V2, V0, V3
+d7a1264a|	VCTZV V2, V3
+d7a12648|	VCTZV V2, V0, V3
+d721274a|	VCPOPV V2, V3
+d7212748|	VCPOPV V2, V0, V3
+d78120d6|	VWSLLVV V1, V2, V3
+d78120d4|	VWSLLVV V1, V2, V0, V3
+d74125d6|	VWSLLVX X10, V2, V3
+d74125d4|	VWSLLVX X10, V2, V0, V3
+d7b127d6|	VWSLLVI $15, V2, V3
+d7b127d4|	VWSLLVI $15, V2, V0, V3
+d7812056|	VROLVV V1, V2, V3
+d7812054|	VROLVV V1, V2, V0, V3
+d7412556|	VROLVX X10, V2, V3
+d7412554|	VROLVX X10, V2, V0, V3
+d7b12752|	VRORVI $15, V2, V3
+d7b12750|	VRORVI $15, V2, V0, V3
+d7812052|	VRORVV V1, V2, V3
+d7812050|	VRORVV V1, V2, V0, V3
+d7412552|	VRORVX X10, V2, V3
+d7412550|	VRORVX X10, V2, V0, V3
+
+# 33.2.2. Zvbc - Vector Carryless Multiplication
+d7a12032|	VCLMULVV V1, V2, V3
+d7a12030|	VCLMULVV V1, V2, V0, V3
+d7612532|	VCLMULVX X10, V2, V3
+d7612530|	VCLMULVX X10, V2, V0, V3
+d7a12036|	VCLMULHVV V1, V2, V3
+d7a12034|	VCLMULHVV V1, V2, V0, V3
+d7612536|	VCLMULHVX X10, V2, V3
+d7612534|	VCLMULHVX X10, V2, V0, V3
+
 # Zvkg - Vector GCM/GMAC
 f7a120b2|	VGHSHVV V1, V2, V3
 f7a128a2|	VGMULVV V2, V3

riscv64/riscv64spec/spec.go

@@ -47,6 +47,8 @@ var extensions = []string{
 	"rv_zvknha",
 	"rv_zvksed",
 	"rv_zvksh",
+	"rv_zvbb",
+	"rv_zvbc",
 	"rv64_a",
 	"rv64_c",
 	"rv64_d",
@@ -332,9 +334,12 @@ func inferFormats(argTypeList []string, op string) string {
 	case op == "VSLL_VI" || op == "VSRL_VI" || op == "VSRA_VI" || op == "VNSRL_WI" ||
 		op == "VNSRA_WI" || op == "VSSRL_VI" || op == "VSSRA_VI" || op == "VNCLIPU_WI" ||
 		op == "VNCLIP_WI" || op == "VSLIDEUP_VI" || op == "VSLIDEDOWN_VI" ||
-		op == "VRGATHER_VI":
+		op == "VRGATHER_VI" || op == "VWSLL_VI":
 		return "arg_vm, arg_vs2, arg_zimm5, arg_vd"
 
+	case op == "VROR_VI":
+		return "arg_vm, arg_vs2, arg_zimm6, arg_vd"
+
 	default:
 		var instStr []string
 		for _, arg := range argTypeList {