Document the FPGA/Verilog backend design (RustHDL/RHDL emission)

[0-jake-0]

What

Adds next/docs/fpga-hdl-backend-decision.md — an exploratory design for a third backend behind the wired-graph front-end of wired-graph-codegen-decision.md (#596): traverse the wired graph, emit RHDL, which emits Verilog, so a graph's hot path (feed handler, signal pipeline) runs on an FPGA while the same wiring backtests in software. Cross-links the two docs both ways.

Docs-only; no code changes. Status recorded in the doc: exploratory, not scheduled — gated strictly behind the software generator's gates plus a hand-written de-risk spike.

What the doc records

• Crate survey: rust-hdl (frozen at 0.46.0, July 2023) vs rhdl (the active pre-release rewrite whose #[kernel] functions compile a Rust subset via its RHIF IR to Verilog — no closures/references). Verdict: prototype on rhdl, ship the emitted Verilog as the toolchain-portable interface.
• Why the mapping is unusually good: the Op pattern is accidentally RTL-shaped (a concept table: tick → valid strobe, Op::State → registers, active edge → valid gating, feedback → registered loop, historical mode → simulation testbench), and func! quotation is exactly the bridge rhdl's no-closure kernels need — quoted bodies splice through as #[kernel] fns with captures as literals, and rhdl's frontend becomes the eligibility checker.
• A worked example end to end: wiring → generated RHDL sketch → idealized Verilog → simulation parity test, showing the filter closure arriving single-sourced while delta needs a hand-written RTL twin.
• The three walls, accepted and documented: fixed-width type dialect (a stricter eligibility tier), per-op RTL twins reintroducing simulation-held drift (with single-sourced scalar-op kernels as the flagship hope), and dependency maturity.
• The gate: a few-days hand-written spike (3–4 op twins, one toy graph, simulate against the interpreted run) that answers the two load-bearing uncertainties before any emitter exists.

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Generated by Claude Code