kernels: fused silu_and_mul + dynamic per-token FP8 quantization#49828
kernels: fused silu_and_mul + dynamic per-token FP8 quantization#49828priyanka25aug wants to merge 1 commit into
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Adds silu_and_mul_dynamic_per_token_quant: a CUDA kernel that fuses SiLU+gating with dynamic per-token FP8 quantization. Unlike silu_and_mul_quant (which requires a pre-calibrated global scale), this kernel derives each token scale from its own activation absmax at runtime -- higher accuracy for W8A8-FP8 MLP inference on variable-range batches. Two-phase kernel (one block per token): Phase 1: silu(gate)*up + block absmax reduction via warp_max + smem. Phase 2: quantize to FP8 using per-token inv_scale. CUDA-only (#ifndef USE_ROCM). ROCm support TBD. Related: Q3 2026 SIG-Quantization roadmap item vllm-project#48168. Signed-off-by: priyanka25aug <priyanka.bajaja@gmail.com>
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@mgoin @yewentao256 — tagging you as quantization/kernel code owners. This adds Key points:
Happy to address any review comments quickly. Could one of you add the |
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Purpose
Adds
silu_and_mul_dynamic_per_token_quant: a fused CUDA kernel that computes SiLU+gating and dynamically quantizes the result to FP8 with a separate scale per token.The gap this fills: the existing
silu_and_mul_quantrequires a pre-calibrated global (per-tensor) scale. For W8A8-FP8 inference, different tokens in the same batch can have very different activation dynamic ranges. This kernel computes each token's scale from its own absmax at runtime, matching the accuracy ofdynamic_per_token_scaled_fp8_quantbut fused with the SiLU gate.Algorithm -- two phases, one kernel launch, one block per token:
Phase 1: Each thread computes
silu(gate[i]) * up[i]and tracks thread-local absmax. Warp-level reduction viawarp_max(__shfl_xor_sync), then cross-warp reduction through shared memory. Thread 0 writesscale[token] = max(absmax, 1e-12) / fp8_max(optionally clamped byscale_ub).Phase 2: Re-reads input, recomputes activation values, quantizes to FP8 via
scaled_fp8_conversion.Reuses existing helpers:
warp_max,scaled_fp8_conversion,quant_type_max_v,VLLM_STABLE_DISPATCH_FLOATING_TYPES,VLLM_STABLE_DISPATCH_FP8_TYPES. CUDA-only (#ifndef USE_ROCM); ROCm support TBD.Test Plan
Parametrized over: tokens in {1, 7, 64, 256}, hidden dim in {64, 512, 4096}, input dtype in {fp16, bf16}, fp8 dtype in {float8_e4m3fn}.
Test Result
Test validates:
(num_tokens, d)and dtypeabsmax / fp8_maxreference (rtol=1e-4)Related: Q3 2026 SIG-Quantization roadmap item #48168 (activation+quant fusions).