[Attention] Enable NVFP4 KV cache on SM120 (consumer Blackwell)#49818
[Attention] Enable NVFP4 KV cache on SM120 (consumer Blackwell)#498180xdespot wants to merge 2 commits into
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Route SM120 (consumer/prosumer Blackwell: 5090, RTX PRO 6000, 5060 Ti) nvfp4 KV cache through XQA decode + fa2 prefill, instead of the SM100-only trtllm-gen path that stock vLLM requires. The dispatch gates are opened for device capability family 120; the decode/cascade wrappers are unchanged. Requires FlashInfer >= 0.6.15, which handles the strided nvfp4 scale-factor / packed KV views natively (flashinfer-ai/flashinfer#3748, vllm-project#3608), so no copy shim is needed. PIECEWISE cudagraph mode is required (see vllm-project#49010). Signed-off-by: 0xdespot <0xdespot@users.noreply.github.com>
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Ran the from-main validation you asked for on an RTX 5090 (SM120). Concurrency question: good news. But NVFP4 KV produces corrupted output on this branch, and FP8 on the identical build does not. (This comment supersedes two earlier ones I posted and removed — a first report from a build I later found invalid, and a retraction I issued too quickly. The invalid build is described under "Methodology" below, because the trap is easy to hit. Everything here is from a build without that flaw.) The findingIdentical prompts,
Every NVFP4 generation: Why this build should be trustworthy
The third row of the table is the important control: the same model, same FlashInfer, same torch, same SM120 card, on an older vLLM base with the equivalent gates, is completely clean. So this isn't NVFP4-on-SM120 being unworkable — something between that base and current main regresses it. Your actual question: no mixed-batch crash8-way concurrency completed with Methodology (worth flagging — it will bite others)My first attempt used I retracted on discovering that — then found the corruption reproduces on the consistent container build above, so the shallow-clone flaw was real but not the cause. Note also that no cu130 wheel exists for this PR's base (or any of the last 25 main commits), so Reprodocker run --rm --gpus all -p 8088:8000 \
-v /path/to/qwen3.6-27b-nvfp4:/model:ro \
-v ./flashinfer_backend.py:/usr/local/lib/python3.12/dist-packages/vllm/v1/attention/backends/flashinfer.py:ro \
-v ./flashinfer_utils.py:/usr/local/lib/python3.12/dist-packages/vllm/utils/flashinfer.py:ro \
vllm/vllm-openai:nightly \
--model /model --kv-cache-dtype nvfp4 --max-model-len 65536 \
--attention-backend flashinfer --gpu-memory-utilization 0.86 \
--max-num-seqs 6 --max-num-batched-tokens 4096 \
--enable-prefix-caching --enable-chunked-prefill \
--language-model-only --skip-mm-profiling \
--compilation-config '{"cudagraph_mode":"PIECEWISE"}'
# one greedy request; then swap --kv-cache-dtype fp8_e4m3 for the controlHappy to bisect between the older working base and Disclosure per AGENTS.md: AI-assisted investigation (Claude). All results produced and verified by me on the hardware described; FP8/NVFP4 comparisons were run back-to-back on one build to isolate the variable. |
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@seanyourhighness Thank you! The FP8 control and the older-base control isolate it: the gates read the pre-refactor NVFP4-KV layout correctly (matches @heungwing's 0.25.1 run) but not main's new Yes please to the bisect... finding the layout-refactor commit is the key. My guess is the SM120 fa2/XQA read (and possibly the strided split-views handling we pass through) needs updating for the new block layout, not the gates themselves. I'll dig into the refactor commit from the code side in parallel and propose how the SM120 path should adapt to the new layout. Marking the PR WIP until we've got it reading the new layout correctly. |
…5-D layout vllm-project#44455 ("[2/N][KV-Cache Layout Refactor]") folded K/V into the content dim (2*num_kv_heads) for every dtype. For NVFP4 the last dim packs [data | scale], so a head-group slice no longer yields the contiguous [data-block | scale-block] region nvfp4_split_data_scale() rebuilds its views from; SM120 fa2/XQA prefill and decode then dequantise against the wrong scales and every generation collapses to token id 0. Gate get_kv_cache_shape and get_kv_cache_stride_order on nvfp4 AND SM120 to retain the pre-refactor 5-D (num_blocks, 2, block_size, num_kv_heads, full_dim) layout. SM100 trtllm-gen keeps the packed layout it was built for - the non-SM120 branches are unreached and unchanged. Adds a pure-CPU shape/stride regression test. Validated on RTX 5090 (SM120): nvfp4 5/5 correct, 8-way concurrency 8/8 (errors=[], 13,158-token needle correct), fp8 output byte-identical to pre-fix. Co-authored-by: seanyourhighness <251925898+seanyourhighness@users.noreply.github.com> Signed-off-by: 0xdespot <0xdespot@users.noreply.github.com>
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What this does
Stock vLLM gates NVFP4 KV cache to SM100 (datacenter Blackwell) only. That path requires trtllm-gen for both prefill and decode, which SM120 (consumer/prosumer Blackwell: RTX 5090, RTX PRO 6000, 5060 Ti) does not have, so on SM120 you hit:
This enables the path in two parts:
(num_blocks, 2, block_size, num_kv_heads, full_dim)layout. [2/N][KV-Cache Layout Refactor] Pack K/V into the content dim across attention backends #44455 folded K/V into the content dim (2*num_kv_heads) for all dtypes; for NVFP4 the last dim packs[data | scale], so a head-group slice no longer yields the contiguous[data-block | scale-block]regionnvfp4_split_data_scale()rebuilds its views from, and SM120 fa2/XQA dequantise against the wrong scales (every generation collapses to token id 0). Gating the shape + stride order on NVFP4 and SM120 restores the correct layout; SM100 trtllm-gen keeps the packed layout it was built for and is not reached.Requirements
max_num_batched_tokens#4044). No copy shim is needed because SM120 retains the 5-D[data | scale]-contiguous layout the NVFP4 consumers require, rather than the post-[2/N][KV-Cache Layout Refactor] Pack K/V into the content dim across attention backends #44455 packed layout.--compilation-config '{"cudagraph_mode":"PIECEWISE"}'.Concurrency
There is a known pitfall in this route: if the fa2 prefill branch rebinds the shared
kv_cache_permutename to thenvfp4_kv_datatuple, the first mixed prefill+decode batch crashes EngineCore ('tuple' object has no attribute 'shape'in the decode stride check). It does not appear under single-stream or prefill-only / decode-only traffic. Root-caused with a 32-way repro by @seanyourhighness.This PR is clean here - the fa2 prefill path binds a local and leaves
kv_cache_permutea Tensor for the decode path. @seanyourhighness confirmed 8/8-way concurrency on a from-main build witherrors=[].Validation
Gates-only on current main produced corrupted NVFP4 output (token-0 collapse) due to the #44455 layout regression above; FP8 on the identical build was clean. @seanyourhighness isolated it causally - reverting only the NVFP4 layout to 5-D, changing nothing else, flipped 5/5 garbage to 5/5 correct - then built and validated the layout fix in this PR.
From-main validation (nightly
0ba2aa35+ these gates + the layout fix, FlashInfer 0.6.15.post1, RTX 5090 / SM120, greedytemperature=0):errors=[], 13,158-token needle correct.Earlier end-to-end coherence was also confirmed on the equivalent 0.25.1 gates by @heungwing (RTX PRO 6000, Hermes Agent / Claude Code) - exact 0.25.1 diff: https://gist.github.com/0xdespot/42600bc72d4623812142c09efcf0e2c9.
Credit
Related: #49011, #49010, #44851, flashinfer-ai/flashinfer#3748 / #3608 / #4044.