Coverage test

[Ha-Sangwoo11]

Summary

1. Add an opt-in VCS + Verdi code coverage flow for the Chisel testbenches
2. Close code coverage for the sideband layer
3. Fix one CDC violation in the sideband layer.

What's included

1. Coverage environment (scala/verdi_coverage/, scala/test/src/UcieSimBackend.scala)

• UCIE_SIM_BACKEND=vcs switches ChiselSim from Verilator to VCS with coverage
  enabled, via an implicit HasSimulator in the test package objects — existing
  tests need no changes. Default behavior is unchanged (Verilator).
• run_verdi_coverage.sh runs the suites, merges the databases per design, and
  writes per-suite reports; view_coverage.sh opens a database in Verdi;
  area_summary.sh maps coverage per subsystem (logphy / sideband / protocol / ...).
• Only the scripts are tracked; all generated output is git-ignored.

2. Sideband coverage closure (SidebandLinkSerdesTest.scala)

• Two scenarios added for the deserializer.
• Sideband is now at 100% line coverage for synthesizable RTL (12/12 modules).

3. CDC fix (SidebandLinkSerdes.scala)

• A Spyglass structural CDC check on SidebandLinkDeserializer flagged the idle
  indication: the combinational counter == 0 output crossed the asynchronous
  forwarded-clock → local-clock boundary directly, so a glitch during a
  multi-bit counter transition could be sampled by the local clock and falsely
  clear the timeout watchdog. Registering it in the source domain confines
  glitches there. Cost is one forwarded-clock cycle on a 512-cycle threshold.