Support for various BF16 and FP8 extensions - #81
Open
zanderdenning wants to merge 5 commits into
Open
Conversation
jerryz123
reviewed
Feb 25, 2026
jerryz123
left a comment
jerryz123
left a comment
Contributor
There was a problem hiding this comment.
Nice! Just a few comments
| FWMSAC.VV, FWMSAC.VF, FWNMSAC.VV, FWNMSAC.VF, | ||
| FREDOSUM.VV, FREDUSUM.VV, FWREDOSUM.VV, FWREDUSUM.VV | ||
| ).map(_.pipelined(depth)).map(_.restrictSEW(1,2,3)).flatten | ||
| ).map(_.pipelined(depth)).map(_.restrictSEW(0,1,2,3)).flatten |
Contributor
There was a problem hiding this comment.
I think technically, this should be controlled by a flag
|
|
||
| def vExts = | ||
| (if (useMxConversion) Seq("zvfofp8min", "zfbfmin", "zvfbfmin", "zvfbfa") else Seq()) ++ | ||
| (if (useMxFPFMA) Seq() else Seq()) |
| object FCVT_SGL extends VectorInstruction { val props = Seq(F6(OPFFunct6.funary0), F3(VectorConsts.OPFVV), RS1(BitPat("b00???")), FPAdd.N, FPMul.N) } | ||
| object FCVT_WID extends VectorInstruction { val props = Seq(F6(OPFFunct6.funary0), F3(VectorConsts.OPFVV), RS1(BitPat("b01???")), Wide2VD.Y, FPAdd.N, FPMul.N) } | ||
| object FCVT_NRW extends VectorInstruction { val props = Seq(F6(OPFFunct6.funary0), F3(VectorConsts.OPFVV), RS1(BitPat("b10???")), Wide2VD.N, Wide2VS2.Y, FPAdd.N, FPMul.N) } | ||
| object FCVT_NRW extends VectorInstruction { val props = Seq(F6(OPFFunct6.funary0), F3(VectorConsts.OPFVV), RS1(BitPat("b1????")), Wide2VD.N, Wide2VS2.Y, FPAdd.N, FPMul.N) } |
Contributor
There was a problem hiding this comment.
You should create 2 variants of this instruction, b11??? and b10???, and add the form based on extension support
Contributor
Author
|
Good catches, these slipped through the change from experimentation to production. This commit should address those. |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Depends on chipsalliance/rocket-chip#3782
This PR adds support for vectorized BF16 and OFP8 to Saturn. These features are disabled by default and enabled with the
useMxFPFMAanduseMxConversionparameters. Below is a full description of which features from each extension are supported.vfwcvtbf16.f.f.wandvfncvtbf16.f.f.wto convert between BF16 and FP32 (however, this is redundant with instructions in Zvfbfa)vfwcvtbf16.f.f.wandvfncvtbf16.f.f.wto convert between OFP8 and BF16vfncvtbf16.sat.f.f.wfor saturating narrowing from BF16 to OFP8vfwmaccbf16.vvfor BF16 to FP32 MACC (however, this is redundant with instructions in Zvfbfa)