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Draft: DRAMSim3 bump - #2334

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jimfangx wants to merge 6 commits into
ucb-bar:mainfrom
jimfangx:dramsim3-bump
Closed

Draft: DRAMSim3 bump#2334
jimfangx wants to merge 6 commits into
ucb-bar:mainfrom
jimfangx:dramsim3-bump

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@jimfangx

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Related PRs / Issues:

Linked PR: ucb-bar/testchipip#274

Type of change:

  • Bug fix
  • New feature
  • Other enhancement

Impact:

  • RTL change
  • Software change (RISC-V software)
  • Build system change
  • Other

Contributor Checklist:

  • Did you set main as the base branch?
  • Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
  • Did you state the type-of-change/impact?
  • Did you delete any extraneous prints/debugging code?
  • Did you mark the PR with a changelog: label?
  • (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
  • (If applicable) Did you add documentation for the feature?
  • (If applicable) Did you add a test demonstrating the PR?
  • (If applicable) Did you mark the PR as Please Backport?

CI Help:
Add the following labels to modify the CI for a set of features.
Generally, a label added only affect subsequent changes to the PR (i.e. new commits, force pushing, closing/reopening).
See ci:* for full list of labels:

  • ci:fpga-deploy - Run FPGA-based E2E testing
  • ci:local-fpga-buildbitstream-deploy - Build local FPGA bitstreams for platforms that are released
  • ci:disable - Disable CI

@jimfangx

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my current dramsim3 stuff (working for verilator & vcs, not tested w/ xcelium) for reference:
https://github.com/jimfangx/chipyard-working/tree/dramsim3-backwards-compatible
https://github.com/jimfangx/testchipip/tree/dramsim3-backwards-compatible
to fall back to dramsim2 in sims, add the USE_DRAMSIM2=1 flag to make run-binary

handed off to another person to work on this, closing this for now

@jimfangx jimfangx closed this Jun 18, 2026
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