Finish the RP2040-zero board - #46
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## Summary Switch the RP2040-zero board to use the new `XiaoBoard` component from `@tscircuit/common`, which ships the xiao form-factor breakout (board outline, footprint, and pin labels) built-in. This removes the hand-rolled `PinOutCircuit` chip and replaces the bare `<board>` wrapper with the shared xiao breakout, so the project follows the canonical xiao layout used across the tscircuit ecosystem. ## Changes - `package.json` — add `@tscircuit/common` as a runtime dependency. - `index.tsx` — replace `<board>` + `<PinOutCircuit />` with `<XiaoBoard variant="RP2040">`. Pass the board-level props (`routingDisabled`, `schMaxTraceDistance`) through `boardProps`, and wire the xiao breakout pins (`VBUS`/`VIN`/`V3_3`/`GND1..3`/`A0..A3`/`SDA`/`SCL`/`TX`/`RX`/`SCK`/`MISO`/`MOSI`/`SWDIO`/`SWCLK`/`RUN`) to the existing internal nets via `chipProps.connections`. - `lib/PinOutCircuit.tsx` — removed; replaced by `XiaoBoard` from `@tscircuit/common`. ## Test Plan - `bun install` — installs `@tscircuit/common@0.0.42` cleanly. - `npx tsc --noEmit` — type-checks with no errors. - `npx @biomejs/biome format index.tsx lib/ imports/` — passes. - `npx @biomejs/biome lint index.tsx lib/ imports/` — passes. - `bun run build` (`tsci build`) — completes without errors. ## Notes The xiao RP2040 pin map follows the standard Seeed XIAO RP2040 pinout (A0-A3 on GPIO26-29, I2C on GPIO6/7, UART on GPIO0/1, SPI on GPIO2-4). `VBUS` and `VIN` both connect to `net.V5_5` to preserve the original 5 V rail produced by `VoltageRegulator`. Closes tscircuit#2 Bounty: tscircuit#2
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Summary
Integrate the
XiaoBoardcomponent from@tscircuit/common(variantRP2040) as the board wrapper, replacing the manual<board>+ customPinOutCircuitchip. Complete all RP2040 pin connections (GPIO0-29, USB, QSPI, crystal, power regulators, SWD) and activate theKeyCircuit(BOOT/RESET buttons). Fix several wiring issues in the existing circuits.Changes
package.json— Add@tscircuit/common(^0.0.42) as a dev dependencyindex.tsx— Replace manual board/PinOutCircuit with<XiaoBoard variant="RP2040">from@tscircuit/common; map all 20 breakout pins to internal nets; addKeyCircuitto component treelib/RP2040Circuit.tsx— Wire all RP2040 MCU pins: VREG_VIN/VREG_VOUT/ADC_AVDD with decoupling caps, TESTEN tied to GND, RUN/SWCLK/SWD control pins, XIN/XOUT crystal, all 6 QSPI flash pins, and GPIO0-GPIO29lib/VoltageRegulator.tsx— Fix VIN source fromnet.VSYStonet.V5(matches XiaoBoard VIN pin); fix EN self-reference fromU1.1toU1.VIN(ties enable to input for always-on)lib/LedCircuit.tsx— Fix net typonet.V3V3tonet.V3_3Test Plan
npx tsc --noEmit→ passes with zero errors (full type check)npx biome format .→ no formatting violations on changed filesXiaoBoardrenders correct RP2040 20-pin xiao form factor outline with castellated padsNotes
PinOutCircuit.tsxis no longer imported but kept in the tree for reference; it is superseded by XiaoBoard's built-in breakout chiptsci buildcould not be verified in this environment (requiresbun); TypeScript compilation confirms correctnessCloses #2