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feat: finish board - add KeyCircuit, fix power/GPIO connections - #40

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pon024587-collab:fix/finish-board-issue-2
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feat: finish board - add KeyCircuit, fix power/GPIO connections#40
pon024587-collab wants to merge 1 commit into
tscircuit:mainfrom
pon024587-collab:fix/finish-board-issue-2

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Closes #2

Changes

  • index.tsx: Added missing KeyCircuit import and component usage. Removed unused RP2040 import. Removed routingDisabled to enable auto-routing.
  • RP2040Circuit.tsx: Added all missing pin connections:
    • VREG_VINnet.V3_3 (power input to internal LDO)
    • VREG_VOUTnet.V1_1 (1.1V output from internal LDO)
    • ADC_AVDDnet.V3_3
    • USB_VDDnet.V3_3
    • TESTENnet.GND (must be tied low per datasheet)
    • RUN, SWCLK, SWD, XIN, XOUT
    • All QSPI pins
    • All GPIO0–GPIO29 pins
  • VoltageRegulator.tsx: Connected EN pin to VIN (always-on), added net.V5 alias.
  • PinOutCircuit.tsx: Unified net.V5_5net.V5 to match other power nets.

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tscircuit Bot requested a deployment to Preview May 16, 2026 19:09 Abandoned
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Finish the RP2040-zero board

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