SPIFFS Bitstreamloader for the Spartan Edge Accelerator Board
High-performance discrete-time voltage-mode PID controller for a 100 kHz synchronous buck converter implemented on a Xilinx Spartan-7 FPGA. Features parallel hardware execution, 23-bit fixed-point precision, dual-stage saturation, and cycle-accurate verification. Validated on physical hardware.
8-bit multiplier module implemented on SystemVerilog meant for the xc7s50csga324-1 Spartan 7 FPGA
A Verilog-based implementation of a 4-bit Binary Coded Hexadecimal to 7-Segment Display Decoder on Spartan-7 FPGA. The design converts binary inputs into human-readable hexadecimal digits (0–F) and displays them in real-time. It includes modular RTL design, simulation, synthesis, and hardware verification using Xilinx Vivado.
This project mainly focuses on building an ALU which performs arithmetic and logic functions using verilog and FPGA
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