Riscv LMUL#2
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- Allow allocating register ranges following LMUL mandates
- For instructions using specifier, merge parts of the logic with the one for LMUL
- Add tests and examples
* Allow allocating register ranges following LMUL mandates * For instructions using <nf> specifier, merge parts of the logic with the one for LMUL * Add tests and examples
…gister extraction - Add early return for simple cases (expansion_factor <= 1) - Extract _extract_base_registers helper function to reduce code duplication - Replace complex nested if-else logic with cleaner helper function calls - Consolidate LMUL and NF instruction writing into unified _write_expanded_instruction - Rename _write_lmul_instruction to _write_expanded_instruction for generality - Simplify _expand_vector_registers_for_nf to auto-infer NF value from instruction The refactoring reduces code complexity while maintaining the same functionality for both LMUL register grouping and NF load/store whole register operations. 🤖 Generated with the help of Claude Code
* Allow allocating register ranges following LMUL mandates * For instructions using <nf> specifier, merge parts of the logic with the one for LMUL * Add tests and examples
…gister extraction - Add early return for simple cases (expansion_factor <= 1) - Extract _extract_base_registers helper function to reduce code duplication - Replace complex nested if-else logic with cleaner helper function calls - Consolidate LMUL and NF instruction writing into unified _write_expanded_instruction - Rename _write_lmul_instruction to _write_expanded_instruction for generality - Simplify _expand_vector_registers_for_nf to auto-infer NF value from instruction The refactoring reduces code complexity while maintaining the same functionality for both LMUL register grouping and NF load/store whole register operations. 🤖 Generated with the help of Claude Code
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…r RISCVVectorIntegerVectorVectorMasked * Needs smae process to be applied for further classes
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When parsing a loop, SLOTHY tries to match any of the available loop types and takes the first that matches. This could lead to the unfortunately situation that a Armv7E-M loop type matches for AArch64 code. For example, previously this code would match a Armv7E-M BranchLoop: count .req x2 mov count, slothy-optimizer#16 start: add x5, x5, x4 add x7, x5, x1 ldr x5, [x0, slothy-optimizer#4] add x5, x5, x7 subs count, count, #2 b.ne start This makes absolutely no sense and would ultimately result in a mysterious error message that b.ne is not a known instruction. This commit fixes that by only trying to parse loop types for the current architecture.
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