Skip to content
View skudlur's full-sized avatar
🦆
Sitting ducks
🦆
Sitting ducks
165 followers · 171 following

Achievements

Achievement: StarstruckAchievement: QuickdrawAchievement: Pull Sharkx2Achievement: YOLO

Achievements

Achievement: StarstruckAchievement: QuickdrawAchievement: Pull Sharkx2Achievement: YOLO

Block or report skudlur

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
skudlur/README.md

Greetings fellow geek 👋

I'm Suhas Kudlur Viswanath—a CPU Researcher @ Huawei in Cambridge, UK, and a recent MSc by Research graduate from the University of Edinburgh.

I specialize in:

Developing RTL for accelerators, RISC-V processors, and interconnects.

Improving memory locality for multi-socket/multi-unit server systems.

Building research tooling in Rust.

Open to collaboration? Yes—whether it's open-source, publications, or a new role. But I'm only interested if the work is offbeat, unique, and actively challenges the norm. Bring me the intriguing, unconventional problems.

Pinned Loading

  1. TraceCXL TraceCXL Public

    TraceCXL is a rapid algorithmic prototyping framework for CXL hardware modeling.

    Python

  2. dma-bsv dma-bsv Public

    Direct Memory Access Controller and Memory Interface

    Bluespec 6

  3. diablo diablo Public

    diablo is an Out-Of-Order 64-bit RISC-V processor.

    C++ 17 4

  4. cayde cayde Public

    cayde is 32-bit RISC-V core written in SystemVerilog

    SystemVerilog 8 8

  5. RISCulator RISCulator Public

    RISCulator is a RISC-V emulator.

    Rust 12

  6. rv-decoder rv-decoder Public

    RISC-V Decoder library for Rust

    Rust 3 1