High‑performance Verilog simulator used to compile and run cycle‑accurate C++ models.
sudo apt update
sudo apt install verilatorWaveform viewer for inspecting dump files generated during simulation.
sudo apt install gtkwaveOpen‑source RTL synthesis framework used to elaborate Verilog designs and produce netlists.
sudo apt install yosysJavaScript runtime and package manager required to run tools like netlistsvg
sudo apt install nodejs npmUtility that converts Yosys JSON netlists into clean and readable SVG schematics.
sudo npm install -g netlistsvgInside your project folder you should have at least the following:
- src/ : contains your .v or .sv source files
- tb/ : contains your .cpp testbenches
- Makefile : type "make help" on terminal to see commands
- auto.tcl : adds first level signals to gtkwave automatically
- (optional) netlist/ : if you use Yosys contains your netlist
This template also includes 2 modules examples and their testbenches.
combinational example:
- nand2.v
- tb_nand2.cpp
sequential example:
- dff_async.v
- tb_dff.cpp
If you already know how to work just delete the examples and keep makefile and other folders.