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MIPS CPU with Pipeline support

Description

Todo

Syntax guide for contributions

  • Use spaces. 4 space tab.
  • When doing if-else statements, you must use begin-end syntax, UNLESS all statements are single line. Keep begin-end consistent, basically.

Good:

if (x) begin
    v = 10;
end
else
    v = 20;
    a = 4;
end
if (p == 2)
    j = 12;
else
    j = 21;

Bad:

if (x)
    v = 10;
else
    v = 20;
    a = 4;
end
  • Inputs always come before Outputs.
  • When naming variables which are present in multiple modules, name them like this: name_modulename. For example: i_fetch, a_decoder. It's confusing otherwise.
  • Do not indent code inside the module block.

Good

module a(...) begin

wire a;
assign a = 2;

end

Bad

module a(...) begin

    wire a;
    assign a = 2;

end

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Verilog implementation of a pipelined MIPS CPU.

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