Ex. No. 6

Date: 19.5.23

Implementation of 4 bit synchronous counters using Verilog HDL

Aim:

To design and implement the following synchronous counters using Verilog HDL.

1. UP counter
2. DOWN counter

Components Required:

1. Laptop with Quartus software and modelsim software.

Theory:

A Synchronous counter is the counter in which the clock input with all the flip-flops uses the same source and produces the output at the same time.

UP Counter

State table

K-map Simplification

Logic Diagram

DOWN Counter

State Table

K-map simplification

Logic Diagram

Procedure:

1. Type the program in Quartus software.
2. Compile and run the program.
3. Generate the RTL schematic and save the logic diagram.
4. Create nodes for inputs and outputs to generate the timing diagram.
5. For different input combinations, generate the timing diagram.

Program:

RTL Schematic:

Timing Diagram:

Result:

Thus the Synchronous UP and DOWN counters using T flipflops are implemented and the state tables are verified.