Riscalar is a highly parameterisable, extensible, and modular computer architecture simulation tool designed for the RISC-V ISA. The ability of Riscalar to explore a large design space with configurable pipeline widths, execution orders, functional units, cache sizes, and branch predictors differentiates it from other RISC-V educational simulators. It is capable of simulating user-designed programs through standard cross-compilation tools, and can be used to explore the relationship between processor microarchitecture, compiler optimizations, and program performance.

Riscalar was created by Josiah Mendes under the supervision of Dr Rajesh C Panicker at the Department of Electrical and Computer Engineering at the National University of Singapore.