Verilog Netlist Transformation (Original vs AI-Refactored)

Overview

This project implements a rule-based transformation of a gate-level Verilog netlist into an equivalent form using a reduced primitive gate basis:

• NAND2X1
• NOR2X1

It includes two implementations:

• Original version (handwritten logic)
• AI-refactored version

Both are executed on the same input netlist and compared for structural equivalence.

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Objective

The goal of this project is to:

• Convert complex logic gates into NAND/NOR-only representations
• Automatically generate intermediate wires
• Normalize gate-level netlists
• Compare two independent implementations
• Validate structural equivalence in real-world transformation

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Supported Gate Transformations

The following gate types are decomposed:

• NAND3XL
• NOR3XL
• CLKINVX1
• INVX2
• OAI22XL
• OAI221X1
• OAI21XL
• OAI211XL
• OAI33X1
• OAI2BB1X1
• OAI2BB2X1
• AOI21X1
• AOI31X1
• AOI32X1
• AOI2BB1X1
• XNOR2XL
• OR2X2
• MXI2XL

All are converted into networks of NAND2X1 and NOR2X1.

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Repository Structure

python-verilog-parser/
├── inputs/
│   └── block32.v
├── outputs/
│   ├── original/
│   │   └── block32_equivalent.v
│   └── ai/
│       └── block32_equivalent.v
├── scripts/
│   ├── original_main.py
│   ├── ai_main.py
│   ├── run_original.sh
│   ├── run_ai.sh
│   └── compare_outputs.sh
├── docs/
└── README.md

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How to Run

Run Original Implementation

./scripts/run_original.sh

Run AI Implementation

./scripts/run_ai.sh

Compare Outputs

./scripts/compare_outputs.sh

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Comparison Summary

Both implementations were executed on:

inputs/block32.v

Key Metrics

Metric	Original	AI Refactored
Source lines	338	335
New wires added	698	697
Output lines	1053	1054
Conversion time	~0.039s	~0.013s
Avg lines/sec	3787	5341

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Differences Observed

Only minor differences were found:

1. Statement Ordering

Example:

// Original
NOR2X1 U39403 ( .A(n789), .B(n398), .Y(n389) );
NAND2X1 U39404 ( .A(n788), .B(n788), .Y(n789) );

// AI
NAND2X1 U39404 ( .A(n788), .B(n788), .Y(n789) );
NOR2X1 U39403 ( .A(n789), .B(n398), .Y(n389) );

This is a producer-consumer ordering difference and does not affect functionality.

2. End-of-file Formatting

-endmodule
\ No newline at end of file
+endmodule

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Important Note on Equivalence

In structural Verilog:

Instance order does NOT define circuit behavior. Connectivity does.

Therefore:

• Reordering of gate instances does not change functionality
• Both outputs are functionally and structurally equivalent

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Conclusion

The original and AI-refactored implementations produce:

• Equivalent NAND/NOR netlists
• Same logical decomposition
• Nearly identical outputs

Differences are limited to:

• Local ordering of generated gates
• Minor formatting variations

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What This Project Demonstrates

• Gate-level logic normalization
• Decomposition into primitive gates
• Automated intermediate wire generation
• Structural equivalence reasoning
• Performance comparison between implementations

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Future Improvements

• Add formal equivalence checking (e.g., Yosys)
• Add simulation-based validation
• Use a proper Verilog parser (AST-based)
• Ensure deterministic output ordering
• Expand gate support coverage

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License

See LICENSE file.