Prepare qcom-next based on tag 'Linux 7.1-rc4' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git#593
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Adreno X2-185 GPU found in Glymur chipsets belongs to the A8x family. It features a new slice architecture with 4 slices, significantly higher bandwidth throughput compared to mobile counterparts, raytracing support, and the highest GPU Fmax seen so far on an Adreno GPU (1850 Mhz), among other improvements. Update the dt bindings documentation to describe this GPU. Link: https://lore.kernel.org/all/20260513-glymur-gpu-dt-v4-2-f83832c3bc9a@oss.qualcomm.com/ Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
…U SMMU Add interconnects property to the common SMMU properties and extend the sm8750 clock description section to also cover Glymur since it uses the same single "hlos" vote clock. Link: https://lore.kernel.org/all/20260513-glymur-gpu-dt-v4-3-f83832c3bc9a@oss.qualcomm.com/ Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
…ap_attach() Commit c7d8100 introduced a brace-less if that skips the dma_buf_map_attachment_unlocked() call when sess->coherent is true, leaving 'table' uninitialized. The unconditional IS_ERR(table) check that follows does not catch NULL, so execution continues with a NULL sg_table, causing a level-0 translation fault when the sgl pointer is dereferenced. Remove the guard; the mapping is always needed to obtain DMA addresses consumed by the rest of the function. Signed-off-by: Anandu Krishnan E <anandu.e@oss.qualcomm.com>
…-reg The pm4125 PMIC uses a different USB VBUS register layout than pm8150b. It uses a 2-bit VBOOST voltage selector supporting output voltages of 4.25 V, 4.5 V, 4.75 V and 5.0 V, instead of a current-limit selector. Move qcom,pm4125-vbus-reg from the pm8150b fallback items list into the standalone enum since the driver handles it with its own match-data and register layout. Make regulator-min/max-microamp conditional so they are only required for current-limit variants (pm8150b, pm6150, pm7250b, pmi632). Add an if/then condition for qcom,pm4125-vbus-reg requiring regulator-min/ max-microvolt instead, and update the pm4125 example accordingly. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
The PM4125 PMIC uses a different register layout for USB VBUS control compared to PM8150B. On PM4125, CMD_OTG is at offset 0x50, OTG_CFG is at 0x56, and offset 0x52 is a 2-bit VBOOST voltage selector rather than a current-limit selector. Introduce per-compatible regulator descriptor data to accommodate these differences. This keeps the existing PM8150B current-limit logic intact while adding a dedicated voltage-selector path for PM4125. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Document shikra compatible for the True Random Number Generator. Link: https://lore.kernel.org/lkml/20260514-shikra_rng-v1-1-4ea721a1429a@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
…ngine Document the crypto engine on the Shikra platform. Link:https://lore.kernel.org/lkml/20260515-shikra_qcrypto-v1-1-80f07b345c29@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Shikra bam dma engine support seven iommu entries. Increase maxItems property for iommus to pass dtbs_check errors. Link: https://lore.kernel.org/lkml/20260515-shikra_qcrypto-v1-2-80f07b345c29@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Document the Inline Crypto Engine (ICE) on the Shikra platform. Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
…sent Some clock controller descriptors do not provide any reset lines. Avoid registering a reset controller when desc->num_resets is zero by making the registration conditional. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Some Qualcomm clock controller descriptors may contain NULL entries in the clk_hws array. Skip such entries when registering clock hardware to avoid passing NULL pointers to the clock framework. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add GCC LPASS clocks support for Qualcomm Shikra SoC. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
The GCC LPASS clocks must be enabled to access audio core clock controller registers. Hence, mark them as critical on Qualcomm Shikra SoCs. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
…ller Add device tree bindings for the Audio Core clock controller on Qualcomm Shikra SoC. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
… SoC Add support for Audio core clock controller on Qualcomm Shikra SoC. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Shikra shares the same power domain topology as sm6125. Remove the dedicated shikra_rpmpds[] and update shikra_desc to reuse sm6125_rpmpds[] with RPM_SMD_LEVEL_TURBO_NO_CPR. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
The display, peripherals (touchpad/touchscreen/keypad), usb and their dependent device nodes are common to both Glymur and Mahua CRDs, so move them from glymur-crd.dts to glymur-crd.dtsi to enable code reuse. Link: https://lore.kernel.org/lkml/20260326-glymur-mahua-common-nodes-v1-1-12bb26920ea4@oss.qualcomm.com/ Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Add remoteproc PAS loader for ADSP and CDSP with its fastrpc nodes. Link: https://lore.kernel.org/lkml/20260325035338.1393287-1-sibi.sankar@oss.qualcomm.com/ Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Enable ADSP and CDSP on Glymur CRD board. Link: https://lore.kernel.org/lkml/20260325035338.1393287-1-sibi.sankar@oss.qualcomm.com/ Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Add LPASS macro codecs and LPASS TLMM pin controller on Qualcomm glymur. for proper sound support. Also add GPR(Generic Pack router) node along with APM(Audio Process Manager) and PRM(Proxy resource Manager) audio services. Link: https://lore.kernel.org/lkml/20260325035338.1393287-5-sibi.sankar@oss.qualcomm.com/ Co-developed-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Add the sound card of Glymur-crd board with the routing for speakers. Add device nodes for the sound support with WSA884x smart speakers and playback via speakers and recording via DMIC microphones. Link: https://lore.kernel.org/lkml/20260325035338.1393287-6-sibi.sankar@oss.qualcomm.com/ Co-developed-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
…Glymur Add the device nodes for the multimedia clock controllers videocc, gpucc and gxclkctl. Link: https://lore.kernel.org/r/20260220-glymur_mmcc_dt_config-v1-1-e0e2f43a32af@oss.qualcomm.com Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Add the nodes to describe the GPU SMMU node. Link: https://lore.kernel.org/all/20260513-glymur-gpu-dt-v4-4-f83832c3bc9a@oss.qualcomm.com/ Signed-off-by: Rajendra Nayak <rajendra.nayak@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
The Adreno X2 series GPU present in Glymur SoC belongs to the A8x family. It is a new HW IP with architectural improvements as well as different set of hw configs like GMEM, num SPs, Caches sizes etc. Add the GPU and GMU nodes to describe this hardware. Link: https://lore.kernel.org/all/20260513-glymur-gpu-dt-v4-5-f83832c3bc9a@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
The GPU does not throttle its speed automatically when it reaches high temperatures. Set up GPU cooling by throttling the GPU speed when it reaches 95°C. Link: https://lore.kernel.org/all/20260513-glymur-gpu-dt-v4-6-f83832c3bc9a@oss.qualcomm.com/ Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Add CoreSight nodes to enable trace paths like TPDM->ETF/STM->ETF. These devices are part of the AOSS, CDSP, QDSS, PCIe5, TraceNoc and some small subsystems, such as GCC, IPCC, PMU and so on. Link: https://lore.kernel.org/all/20260318-add-coresight-dt-nodes-for-glymur-v2-1-d76e08f21fa5@oss.qualcomm.com/ Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Describe PCIe3a controller and PHY. Also add required system resources like regulators, clocks, interrupts and registers configuration for PCIe3a. Link: https://lore.kernel.org/all/20260304-glymur_gen5x8_phy-v1-5-849e9a72e125@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Add embedded controller node for Glymur CRDs which adds fan control, temperature sensors, access to EC state changes through SCI events and suspend entry/exit notifications to the EC. Link: https://lore.kernel.org/lkml/20260313-v04-add-driver-for-ec-v4-3-ca9d0efd62aa@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
…r PCIe PHY on Glymur Add refgen and qref power supplies in each pcie phy devicetree node. For some instance, refgen and qref may share LDOs with phy LDOs, so add additional power supplies. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Switch opp entry for dispcc to turbo Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
# Conflicts: # drivers/media/platform/qcom/iris/iris_firmware.c # drivers/media/platform/qcom/venus/firmware.c # drivers/remoteproc/qcom_q6v5_pas.c # drivers/soc/qcom/ice.c # drivers/soc/qcom/mdt_loader.c # include/linux/soc/qcom/mdt_loader.h
# Conflicts: # arch/arm64/boot/dts/qcom/kaanapali.dtsi
# Conflicts: # drivers/phy/qualcomm/phy-qcom-qmp-pcie.c # include/linux/firmware/qcom/qcom_scm.h
# Conflicts: # drivers/firmware/qcom/Makefile
# Conflicts: # drivers/remoteproc/qcom_q6v5_pas.c # drivers/soc/qcom/smem.c
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
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Name SHA Commits
tech/bsp/clk eea3e98 11
tech/bsp/devfreq a0c2f21 6
tech/bsp/ec 643c24b 2
tech/bsp/soc-infra 20c09ce 3
tech/bsp/pinctrl 3f1acf8 1
tech/bsp/remoteproc a7b9b6d 10
tech/bus/peripherals 287f0f5 8
tech/bus/pci/all c266573 14
tech/bus/pci/phy aaf8ef1 4
tech/bus/usb/dwc 49ac8e0 2
tech/bus/usb/phy 8c7f91d 35
tech/debug/hwtracing 25c6a74 30
tech/pmic/misc eee20da 1
tech/mem/iommu 1fa98cb 5
tech/mm/audio/all cab3357 10
tech/mm/camss 147ae87 28
tech/mm/drm 2fbdd74 60
tech/mm/fastrpc e0ba718 9
tech/mm/phy 56ccbf4 1
tech/mm/video 8bbe314 36
tech/mm/gpu 8a269bc 3
tech/net/ath 3623de0 13
tech/net/phy a3602e9 1
tech/net/bluetooth 9cca493 2
tech/pm/power 2d42c35 9
tech/pm/thermal 90f2db5 5
tech/security/crypto f030676 14
tech/security/ice 1564b82 25
tech/security/optee cee615a 21
tech/storage/phy cf1667f 1
tech/storage/all e254dae 1
tech/all/dt/qcs6490 5828ac7 17
tech/all/dt/qcs9100 8a00fd7 17
tech/all/dt/qcs8300 ffd35fe 16
tech/all/dt/qcs615 9e2f111 9
tech/all/dt/agatti c828f10 1
tech/all/dt/hamoa 670d002 29
tech/all/dt/glymur bd03470 27
tech/all/dt/kaanapali 7436a08 9
tech/all/dt/pakala 705ac54 6
tech/all/config ff67f6a 61
tech/overlay/dt c6232b6 46
tech/all/workaround d15f5a1 15
tech/mproc/all 0aa90b7 3
tech/noup/debug/all d2b684d 25
tech/hwe/unoq b2ea57b 5
early/hwe/shikra/drivers 3aa65ff 84
early/hwe/shikra/dt 919fd6c 61