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41 changes: 31 additions & 10 deletions Cargo.lock

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2 changes: 1 addition & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ log = { version = "0.4.27", default-features = false }
pin-project-lite = "0.2.13"
toml = ">=0.5.0, <0.9.0"
tokio = "1.33"
rand = { version = "0.8.5", default-features = false }
rand = { version = "0.9.4", default-features = false }
serde = { version = "1.0.192", features = ["derive"] }
serde_json = { version = "1.0.111" }
serde_test = { version = "1.0.176" }
Expand Down
8 changes: 4 additions & 4 deletions fuzz/Cargo.lock

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2 changes: 1 addition & 1 deletion statime-linux/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ log = { workspace = true, default-features = true }
pin-project-lite.workspace = true
toml.workspace = true
tokio = { workspace = true, features = ["net", "rt-multi-thread", "time", "macros", "sync", "io-util"] }
rand = { workspace = true, default-features = false, features = ["std", "std_rng"] }
rand = { workspace = true, default-features = false, features = ["std", "std_rng", "os_rng"] }
serde.workspace = true
serde_json.workspace = true

Expand Down
2 changes: 1 addition & 1 deletion statime-linux/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -368,7 +368,7 @@ async fn actual_main() {
HardwareClock::None => add_sw_clock(&mut clock_port_map),
};

let rng = StdRng::from_entropy();
let rng = StdRng::from_os_rng();
let port = instance.add_port(
port_config.into(),
KalmanConfiguration::default(),
Expand Down
14 changes: 10 additions & 4 deletions statime-stm32/Cargo.lock

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2 changes: 1 addition & 1 deletion statime/src/config/port.rs
Original file line number Diff line number Diff line change
Expand Up @@ -102,7 +102,7 @@ impl<A> PortConfig<A> {
/// For more information see *IEEE1588-2019 section 9.2.6.12*
pub fn announce_duration(&self, rng: &mut impl Rng) -> core::time::Duration {
// add some randomness so that not all timers expire at the same time
let factor = 1.0 + rng.sample::<f64, _>(rand::distributions::Open01);
let factor = 1.0 + rng.sample::<f64, _>(rand::distr::Open01);
let duration = self.announce_interval.as_core_duration();

duration.mul_f64(factor * self.announce_receipt_timeout as u32 as f64)
Expand Down
39 changes: 31 additions & 8 deletions statime/src/port/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -118,7 +118,6 @@ pub(crate) mod state;
/// # }
/// # }
/// # let (instance_config, time_properties_ds) = unimplemented!();
/// use rand::thread_rng;
/// use statime::config::{AcceptAnyMaster, DelayMechanism, PortConfig, PtpMinorVersion};
/// use statime::filters::BasicFilter;
/// use statime::PtpInstance;
Expand All @@ -140,7 +139,13 @@ pub(crate) mod state;
/// };
/// let filter_config = 1.0;
/// let clock = system::Clock {};
/// let rng = thread_rng();
/// # struct MockRng(u64);
/// # impl rand::RngCore for MockRng {
/// # fn next_u32(&mut self) -> u32 { self.next_u64() as u32 }
/// # fn next_u64(&mut self) -> u64 { self.0 = self.0.wrapping_add(1); self.0 }
/// # fn fill_bytes(&mut self, dest: &mut [u8]) { for chunk in dest.chunks_mut(8) { let b = self.next_u64().to_le_bytes(); chunk.copy_from_slice(&b[..chunk.len()]); } }
/// # }
/// let rng = MockRng(0);
///
/// let port_in_bmca = instance.add_port(port_config, filter_config, clock, rng);
///
Expand Down Expand Up @@ -722,6 +727,24 @@ mod tests {
};

// General test infra
pub(super) struct MockRng(u64);

impl rand::RngCore for MockRng {
fn next_u32(&mut self) -> u32 {
self.next_u64() as u32
}
fn next_u64(&mut self) -> u64 {
self.0 = self.0.wrapping_add(1);
self.0
}
fn fill_bytes(&mut self, dest: &mut [u8]) {
for chunk in dest.chunks_mut(8) {
let bytes = self.next_u64().to_le_bytes();
chunk.copy_from_slice(&bytes[..chunk.len()]);
}
}
}

pub(super) struct TestClock;

impl Clock for TestClock {
Expand Down Expand Up @@ -749,7 +772,7 @@ mod tests {

pub(super) fn setup_test_port(
state: &RefCell<PtpInstanceState>,
) -> Port<'_, Running, AcceptAnyMaster, rand::rngs::mock::StepRng, TestClock, BasicFilter> {
) -> Port<'_, Running, AcceptAnyMaster, MockRng, TestClock, BasicFilter> {
let port = Port::<_, _, _, _, BasicFilter>::new(
state,
PortConfig {
Expand All @@ -767,7 +790,7 @@ mod tests {
0.25,
TestClock,
Default::default(),
rand::rngs::mock::StepRng::new(2, 1),
MockRng(0),
);

let (port, _) = port.end_bmca();
Expand All @@ -777,7 +800,7 @@ mod tests {
pub(super) fn setup_test_port_custom_identity(
state: &RefCell<PtpInstanceState>,
port_identity: PortIdentity,
) -> Port<'_, Running, AcceptAnyMaster, rand::rngs::mock::StepRng, TestClock, BasicFilter> {
) -> Port<'_, Running, AcceptAnyMaster, MockRng, TestClock, BasicFilter> {
let port = Port::<_, _, _, _, BasicFilter>::new(
state,
PortConfig {
Expand All @@ -795,7 +818,7 @@ mod tests {
0.25,
TestClock,
port_identity,
rand::rngs::mock::StepRng::new(2, 1),
MockRng(0),
);

let (port, _) = port.end_bmca();
Expand All @@ -805,7 +828,7 @@ mod tests {
pub(super) fn setup_test_port_custom_filter<F: Filter>(
state: &RefCell<PtpInstanceState>,
filter_config: F::Config,
) -> Port<'_, Running, AcceptAnyMaster, rand::rngs::mock::StepRng, TestClock, F> {
) -> Port<'_, Running, AcceptAnyMaster, MockRng, TestClock, F> {
let port = Port::<_, _, _, _, F>::new(
state,
PortConfig {
Expand All @@ -823,7 +846,7 @@ mod tests {
filter_config,
TestClock,
Default::default(),
rand::rngs::mock::StepRng::new(2, 1),
MockRng(0),
);

let (port, _) = port.end_bmca();
Expand Down
4 changes: 2 additions & 2 deletions statime/src/port/slave.rs
Original file line number Diff line number Diff line change
Expand Up @@ -495,7 +495,7 @@ impl<A, C: Clock, F: Filter, R: Rng, S: PtpInstanceStateMutex> Port<'_, Running,
response_recv_time: None,
};

let random = self.rng.sample::<f64, _>(rand::distributions::Open01);
let random = self.rng.sample::<f64, _>(rand::distr::Open01);
let factor = random * 2.0f64;
let duration = log_min_pdelay_req_interval
.as_core_duration()
Expand Down Expand Up @@ -545,7 +545,7 @@ impl<A, C: Clock, F: Filter, R: Rng, S: PtpInstanceStateMutex> Port<'_, Running,
recv_time: None,
};

let random = self.rng.sample::<f64, _>(rand::distributions::Open01);
let random = self.rng.sample::<f64, _>(rand::distr::Open01);
let factor = random * 2.0f64;
let duration = log_min_delay_req_interval
.as_core_duration()
Expand Down
8 changes: 7 additions & 1 deletion statime/src/ptp_instance.rs
Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,13 @@ use crate::{
/// # let port_config: statime::config::PortConfig<AcceptAnyMaster> = unimplemented!();
/// # let filter_config = unimplemented!();
/// # let clock: MockClock = unimplemented!();
/// # let rng: rand::rngs::mock::StepRng = unimplemented!();
/// # struct MockRng(u64);
/// # impl rand::RngCore for MockRng {
/// # fn next_u32(&mut self) -> u32 { self.next_u64() as u32 }
/// # fn next_u64(&mut self) -> u64 { self.0 = self.0.wrapping_add(1); self.0 }
/// # fn fill_bytes(&mut self, dest: &mut [u8]) { for chunk in dest.chunks_mut(8) { let b = self.next_u64().to_le_bytes(); chunk.copy_from_slice(&b[..chunk.len()]); } }
/// # }
/// # let rng: MockRng = unimplemented!();
/// #
/// use statime::PtpInstance;
/// use statime::config::{AcceptAnyMaster, ClockIdentity, ClockQuality, InstanceConfig, TimePropertiesDS, TimeSource};
Expand Down
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