Micro optimizations#8
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mbedTLS v4 (ESP-IDF >= 6.0) moved the legacy one-shot mbedtls_sha256() to a private header, which forced a separate mbedtls_compat shim component. Use the public PSA hash API (psa_hash_compute) instead, so the component builds on current ESP-IDF with just REQUIRES mbedtls. Keep the cUR API and ABI unchanged: ur_sha256() initializes PSA before hashing and aborts on PSA backend failures, matching the existing void-return contract instead of adding a new init entry point.
Use a generated static const slice-by-8 table for CRC32. On ESP32-P4 this measured ~2.7x faster than the nibble table (19.1 -> 7.2 cycles/byte), at the cost of about 8 KB of flash. Default the fast path on for host and ESP-IDF builds; set UR_CRC32_SLICE_BY_8=0 on the Makefile build or disable CONFIG_UR_CRC32_SLICE_BY_8 in ESP-IDF for the small table.
…oder with ur_xor_inplace()/ur_xor() helpers that XOR 8 bytes per iteration (scalar tail). ~4.3x faster on ESP32-P4 (7.0 -> 1.6 cycles/byte).
Add an ESP32-P4 (xesppie) 128-bit vector path to ur_xor_inplace/ur_xor: scalar head to reach 16-byte alignment, esp.vld/esp.xorq/esp.vst on aligned 16-byte blocks, word-wise fallback when the buffers are not co-aligned. ~0.45 cycles/byte on aligned runs 15.7x over the original byte loop. ~3.6x over the word-wise path. ESP32-P4 only, off by default.
Exercise both optimized and fallback paths in CI.
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Includes #7
Adds some optional micro optimizations for CRC/XOR, some ESP32P4 specific, open to feedback and happy to drop any commit if it doesn't make sense/not worth the complexity.
The speed ups are measured on an esp32p4 and are nice but in the grand scheme of things these optimizations are not really saving much right now - it seems a lot of the time when benchmarking is spent in malloc - but any change to that requires a lot more changes/testing on all supported platforms so left it for another time/PR.