Rebase NI nilrt/master/6.12 commits onto nilrt/master/6.18

.github/workflows/pr-checks.yml

@@ -0,0 +1,48 @@
+name: PR Checks
+
+on:
+  pull_request: {}
+  workflow_dispatch: {}
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+
+    steps:
+      - uses: actions/checkout@v4
+        with:
+          ref: ${{ github.event.pull_request.head.sha }}
+          fetch-depth: 100
+
+      - name: Fetch base_ref
+        run: git -c protocol.version=2 fetch --no-tags --prune --no-recurse-submodules --depth=1 origin ${{ github.base_ref }}
+
+      - name: Install build dependencies
+        run: |
+          sudo apt update
+          sudo apt install libelf-dev
+          sudo apt install python3-ply
+          sudo apt install python3-git
+
+      - name: "[TEST] Build nati_x86_64_defconfig"
+        run: |
+          make nati_x86_64_defconfig
+          make -j8 bzImage modules
+
+      - name: "[TEST] Does nati_x86_64_defconfig need update"
+        run: |
+          make savedefconfig
+          diff defconfig arch/x86/configs/nati_x86_64_defconfig
+
+      - name: "[TEST] Is rebase required"
+        run: |
+          common_ancestor=$(git merge-base HEAD origin/${{ github.base_ref }})
+          base_ref_head=$(git log -1 --format=%H origin/${{ github.base_ref }})
+
+          [ $common_ancestor == $base_ref_head ]
+
+      - name: "[TEST] Run checkpatch.pl"
+        run: |
+          common_ancestor=$(git merge-base HEAD origin/${{ github.base_ref }})
+          git format-patch $common_ancestor
+          ./scripts/checkpatch.pl *patch

Documentation/devicetree/bindings/serial/ni,ni16550.yaml

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+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/ni,ni16550.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NI 16550 asynchronous serial interface (UART)
+
+maintainers:
+  - Brenda Streiff <brenda.streiff@ni.com>
+
+allOf:
+  - $ref: serial.yaml#
+
+properties:
+  compatible:
+    const: ni,ni16550
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  ni,serial-port-mode:
+    description: Indicates whether this is an RS-232 or RS-485 serial port.
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [ RS-232, RS-485 ]
+    default: RS-485
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    serial@80000000 {
+      compatible = "ni,ni16550";
+      reg = <0x80000000 0x8>;
+      interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
+      clocks = <&clk_uart>;
+      ni,serial-port-mode = "RS-232";
+    };
+...

arch/arm/boot/dts/xilinx/ni-793x.dts

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+/dts-v1/;
+/include/ "ni-zynq.dtsi"
+
+/* NIDEVCODE 77AC */
+/* NIDEVCODE 77B2 */
+/* NIDEVCODE 77B1 */
+
+/ {
+	model = "NI-793x";
+	compatible = "ni,zynq", "xlnx,zynq-7000";
+
+	amba@0 {
+
+		leds-ni793x@4020F000 {
+			compatible = "ni,led-793x";
+			reg = <0x4020F000 4>;
+			user1 {
+				label = "nilrt:user1:green";
+			};
+		};
+
+		i2c0: i2c@e0004000 {
+			nicpld@40 {
+				watchdogs {
+					boot-watchdog {
+						interrupt-parent = <&gpio>;
+						interrupts = <15 2 /* IRQ_TYPE_EDGE_FALLING */>;
+					};
+				};
+
+				leds {
+					status-0 {
+						label = "nilrt:status:yellow";
+						max-brightness = <0xFFFF>;
+					};
+					eth0-0 {
+						label = "nilrt:eth0:green";
+						linux,default-trigger =
+						  "e000b000.etherne:00:100Mb";
+					};
+					eth0-1 {
+						label = "nilrt:eth0:yellow";
+						linux,default-trigger =
+						  "e000b000.etherne:00:Gb";
+					};
+				};
+			};
+
+			ds3231_rtc@68 {
+				status = "okay";
+			};
+		};
+	};
+};
+
+&gem0 {
+	status = "okay";
+
+	/* No fpga_clk specified because we want our FPGA clock
+	 * (fclk0) to always be 125 MHz. The bootloader sets
+	 * fclk0 to 125 MHz and we just leave it like that. */
+
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	#address-cells = <0x1>;
+	#size-cells = <0x0>;
+
+	emio-speed-gpios = <0>,
+			   <&gpio 54 0>;
+
+	phy0: phy@0 {
+		compatible = "micrel,KSZ9031";
+		device_type = "ethernet-phy";
+		reg = <0x0>;
+		/* Interrupt on GPIO1. */
+		interrupts = <1 8 /* IRQ_TYPE_LEVEL_LOW */>;
+		interrupt-parent = <&gpio>;
+
+		/* Set RX_CLK Pad Skew [4:0] to 0b00000. */
+		rxc-skew-ps = <0>;
+	};
+};
+
+&sdhci0 {
+	status = "okay";
+};
+
+&ni_uart0 {
+	status = "okay";
+	transceiver = "RS-232";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "peripheral";
+};
+
+&usb1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&clkc {
+	/* Enable fclk0 for eth0 and eth1, fclk1 for serial. */
+	fclk-enable = <0x3>;
+};

arch/arm/boot/dts/xilinx/ni-bluefin.dts

@@ -0,0 +1,147 @@
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+/include/ "ni-zynq.dtsi"
+
+/* NIDEVCODE 78C7 */
+/* NIDEVCODE 78B9 */
+
+/ {
+	model = "NI Bluefin";
+	compatible = "ni,zynq", "xlnx,zynq-7000";
+
+	leds {
+		compatible = "gpio-leds";
+
+		/* LED_STATUSy on GPIO46 */
+		status {
+			label = "nilrt:status:yellow";
+			gpios = <&gpio0 46 0>;
+			default-state = "on";
+		};
+
+		/* LED_ACTIVEg on GPIO47 */
+		active {
+			label = "nilrt:active:green";
+			gpios = <&gpio0 47 0>;
+			default-state = "off";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* Reset switch is on GPIO48 */
+		reset_sw@0 {
+			label = "reset_sw";
+			gpios = <&gpio0 48 1 /* GPIO_ACTIVE_LOW */>;
+			linux,code = <408>; /* KEY_RESTART */
+			gpio-key,wakeup;
+		};
+	};
+
+	gpio_restart {
+		compatible = "gpio-restart";
+
+		/* ~PS_FORCE_RESET is on GPIO44 */
+		gpios = <&gpio0 44 1 /* GPIO_ACTIVE_LOW */>;
+		priority = <200>;
+	};
+};
+
+&i2c0 {
+	/* Override ni-zynq.dtsi; we do not have a CPLD at 0x40. */
+	nicpld@40 {
+		status = "disabled";
+	};
+
+	tmp451@4C {
+		compatible = "ti,tmp451";
+		reg = <0x4C>;
+		vcc-supply = <&regulator_vccpint>;
+	};
+};
+
+&gem0 {
+	status = "okay";
+	#address-cells = <0x1>;
+	#size-cells = <0x0>;
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+		reg = <0>;
+	};
+
+	mdio0: mdio {
+		status = "okay";
+	};
+};
+
+&mdio0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	switch: switch@0 {
+		compatible = "marvell,mv88e6085";
+		reg = <0x0>;
+		status = "okay";
+		interrupt-parent = <&intc>;
+		interrupts = <45 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "cpu";
+				phy-mode = "rgmii-id";
+				ethernet = <&gem0>;
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "sw0";
+				phy-handle = <&swphy1>;
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "sw1";
+				phy-handle = <&swphy2>;
+			};
+		};
+
+		mdio {
+			swphy1: ethernet-phy@11 {
+				reg = <0x11>;
+			};
+
+			swphy2: ethernet-phy@12 {
+				reg = <0x12>;
+			};
+		};
+	};
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&watchdog0 {
+	status = "okay";
+	reset-on-timeout;
+};