add a generic JLinkProgrammer and use it for SAM4L#489
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- add access to min and max VCC values - add optional XADC logging to test_husky.py to help diagnose temperature and supply issues
- allow for pattern size > 128 bytes - obtain latency property from an FPGA register instead of hard-coding it here (backwards compatible, so older bitfiles will still function correctly)
Also fixed some inadvertent copy/paste errors for clock setup for the SAD tests.
Add N76E003 firmware
merging develop
WIP as current usefulness is low.
Renamed from test_s6_glitch.py, because it now does more than glitch testing: it also checks the CW generated clock.
Includes fixes around building CW-Pro bitfile.
update fpga-updates from develop
Well tested by tests/test_s6.py; confident that double glitches are no longer a thing.
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A generic
JLinkProgrammerclass has been added. Its constructor takes a core as an argument. This makes it easy to add a Programmer for any processor supported by JLink.Next to this a
SAM4LProgrammerclass has been added which usesJlinkProgrammer("ATSAM4LC2AA")and specifically targets the CW308_SAM4L board.With the following small addition to https://github.com/newaetech/chipwhisperer-jupyter/blob/3f2796fc38450777b4f16c1a3f04b0e9fd1b7433/Setup_Scripts/Setup_Generic.ipynb it becomes possible to run most of the courses on the CW308_SAM4L board by attaching a JLink and only changing
PLATFORM = 'CW308_SAM4L':