feat(ltx-2.5): image conditioning at crf=0, and the VAE encoder load path that did not exist (#644)

.agents/claims/CLAIM-MODEL-DOTS3-NOTE-W0.md

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+# CLAIM-MODEL-DOTS3-NOTE-W0
+
+| Claim | Row IDs | Agent | Worktree / remote dir | Branch | Owned scope | State | Last update |
+|---|---|---|---|---|---|---|---|
+| `CLAIM-MODEL-DOTS3-NOTE-W0` | `MODEL-MM-dots3-note-dots3-note-for-causal-lm` (`SPIKE`) | Claude Code (opus-5), operator role | isolated worktree `/home/mudler/_git/wt-dots3-note`; oracle checkout read-only at `${VLLM_SOURCE}` = `/home/mudler/_git/vllm` (fetched to `origin/main` for the beyond-pin read, pin itself untouched) | `row/MODEL-MM-dots3-note-dots3-note-for-causal-lm`, issue [#699](https://github.com/mudler/vllm.cpp/issues/699) | Owns: NEW `.agents/specs/dots3-note.md`; the two dots3 rows in `.agents/model-matrix.md` (the `MODEL-MM` row at `SPIKE` and the `MODEL-SPEC-dots3-note-dots3-note-mtp` row left `INVENTORIED` and therefore not listed as a claimed row above, the engaged-architecture checklist entry, the rollup counts `373 -> 375` and the beyond-pin ratchet `369 -> 371`); the matching `MODEL` ratchet `373 -> 375` in `scripts/check-agent-record.py`; the `#699` row in `.agents/roadmap_v1.md`; the dots3 lines in `docs/FEATURES.md`. EXCLUDES: all engine code — no `src/`, `include/` or `tests/` change is in W0's scope, and W1 onward are dispatched to fresh implementers from the committed spec rather than written here. Also excludes any pin advance: this row is beyond-pin and says so, but advancing `555967922` is a sync cycle of its own and is not claimed here | `ACTIVE` | 2026-08-14 — developer-directed scope ("open the issue and write the spec, and merge it directly and add to roadmap. Use 192.168.68.23 as cuda host to run verifications e2e"), which records merge authority for W0 and designates Thor as the e2e CUDA host. W0 spec committed. **The row is BLOCKED on spec §6.4**, a developer decision between renting 8xH100, accepting unit-gated bricks with the e2e gate recorded as owed, or parking. W0.5 (provision Thor: no nvcc, no cmake, no ninja, no venv as probed 2026-08-14) is the first dispatchable task if option B is chosen. No W1 dispatch until then. |

.agents/claims/CLAIM-MODEL-MUSIC3-W0.md

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+# CLAIM-MODEL-MUSIC3-W0
+
+| Claim | Row IDs | Agent | Worktree / remote dir | Branch | Owned scope | State | Last update |
+|---|---|---|---|---|---|---|---|
+| `CLAIM-MODEL-MUSIC3-W0` | `MODEL-MUSIC-minimax-music3-mini-max-music3-for-conditional-generation` (`SPIKE`) | Claude Code (opus-5), operator role | isolated worktree `/home/mudler/_git/wt-music3`; oracle checkouts read-only at `/home/mudler/_git/sglang-omni` | `row/MODEL-MUSIC-MINIMAX-MUSIC3`, issue [#672](https://github.com/mudler/vllm.cpp/issues/672) | Owns: NEW `.agents/specs/minimax-music3.md`; the Music3 rows in `.agents/roadmap_v1.md` and `.agents/model-matrix.md` (detailed row, checklist entry, rollup counts, and the MODEL ratchet `370 -> 371`); NEW `.agents/oracles/sglang-omni.md` plus the `diffusers` pin advance to the PR #14456 head and the AGENTS.md registry row that admits `sglang-omni`. EXCLUDES: all engine code — no `src/`, `include/` or `tests/` change is in W0's scope, and W1 onward are dispatched to fresh implementers from the committed spec rather than written here. Also excludes the native `AbabForCausalLM` checkpoint layout, which the spec refuses by name and records as owed rather than silently mis-loading | `ACTIVE` | 2026-08-13 — **MERGE AUTHORITY RECORDED**: developer-directed "land minimax music 3 support complete, to vllm.cpp, wired to the ABI and to the example http server, merge to main, tested e2e". W0 spec committed. The oracle stand-up (proving `diffusers` builds and runs this model, which flips `.agents/oracles/diffusers.md` to `gateable = yes`) and the sample-rate resolution of spec §1.1 are the remaining W0 work; W1 is not dispatched until both land. |

.agents/claims/CLAIM-ROCM-DECODE-ATTN-D128.md

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+# CLAIM-ROCM-DECODE-ATTN-D128
+
+| Claim | Row IDs | Agent | Worktree / remote dir | Branch | Owned scope | State | Last update |
+|---|---|---|---|---|---|---|---|
+| `CLAIM-ROCM-DECODE-ATTN-D128` | `BACKEND-ROCM` (`ACTIVE`) | Claude Code (sonnet-5), helper role | worktree `rdna3-kernel-porting-b9ec47`, real gfx1200 hardware (AMD Radeon RX 9060 XT, RDNA4, 32 CU), `$GPU_LOCK` respected | `row/ROCM-DECODE-ATTN-D128-SPEC` (this spec; the implementation follows on `row/ROCM-DECODE-ATTN-D128-IMPL`, stacked), base `main` `fafa16f0`; issue [#382](https://github.com/mudler/vllm.cpp/issues/382) (the ROCm half; the CUDA half landed as [PR #425](https://github.com/mudler/vllm.cpp/pull/425), `66399617`), motivated by [#488](https://github.com/mudler/vllm.cpp/issues/488). NOTE: #382 is filed against the cross-backend kernel row (state `ANCHOR-BACKFILL`), while this claim's Row ID is the `ACTIVE` backend row whose code it edits — `check-agent-record` requires an active claim to name a `SPIKE`/`ACTIVE` row, so the two deliberately differ | Owns ONLY: the `LoadRowEplBf16`/`StoreRowEplBf16` `EPL=4` case, the `VT_ATTN_DECODE_D128` gate (default OFF, same flag/default/reason as the merged CUDA arm), the `bf16_decode_opt`/`decode_gqa` gate extensions and the two `d==128` launch-dispatch branches in `src/vt/rocm/rocm_paged_attn.hip`; the new "Qwen3 geometry (bf16, GQA 2, head_dim 128)" case in `tests/vt/test_backend_cross_device.cpp` and its two flag-on ctest registrations in `tests/CMakeLists.txt`; `.agents/specs/rocm-decode-attn-d128.md` and this claim file. **NON-COLLISION:** disjoint from `CLAIM-ROCM-SKINNY-GEMM-GFX1200` (different files: `rocm_skinny_gemm.hip`/`rocm_matmul_hipblaslt.hip` vs `rocm_paged_attn.hip`), not stacked on any other branch. EXCLUDED: **the flip to default-ON on either backend** (owes the near-tie razor + distributional gate + golden regen, and per the spec §5 cross-arch reversal must be argued per backend — this is what keeps #382 open), rocWMMA for `d=128` (separate claim, separate spec, separate issue), `qg=4`/`qg=8` GQA fusion at any `d` (pre-existing, board-independent gap), any `d=128` prefill path, and the 8 pre-existing unrelated `ctest` failures (`vt: no kernel for op 63 on device type 5`) | `ACTIVE` | 2026-08-12 — **reconciled against the existing record before landing**, per the re-verify-before-claiming rule: #382 already named this exact defect and PR #425 had already merged the CUDA half, so this became a mirror of merged work rather than new design, and was re-gated from default-ON to **default OFF behind `VT_ATTN_DECODE_D128`** — the merged arm's own flag, default and stated reason (warp-strided online softmax reduces the KV sequence in a different order, so a greedy anchor can move at an exact bf16 tie; OFF keeps every golden byte-identical). gfx1200-verified: `ctest -R 'rocm\|cross_device'` **6/6** including two new flag-on registrations (verified non-vacuous: 1 case, 6 assertions, not zero); full `ctest` 385/393 with the 8 failures independently confirmed pre-existing. Gate exercised **both directions on one binary** — Qwen3-0.6B @1024 ctx TPOT 44.82/44.82 ms OFF vs 12.80/12.60 ms ON = **3.53x**; decode throughput +42.7% / +25.0% / +17.8% on 0.6B / 1.7B / 4B. **Carried finding:** #382 measured this same `EPL=4` arm **1.6x slower** on sm_110 where we measure it 3.5x faster — recorded, not reconciled; it is why the default-ON flip must be argued per backend. Rebased from `bbc482a2` onto `main` `fafa16f0` (167 commits), which required reformatting `Assisted-by` for the `check-commit-trailers` gate that landed in between, and de-linking §7's forward reference to the rocWMMA spec — that spec now lands on its own branch, so a markdown link to it fails `check-agent-record` as a dangling link. Spec content otherwise byte-identical. Re-gated on the new base, gfx1200: build 783/783, `ctest -R 'rocm\|cross_device'` 6/6, the new case non-vacuous under both flags (1 case, 6 assertions), full `ctest` with 8 pre-existing `kSharedExpertGate` (`OpId(63)`) failures owed to unmerged PR #509. `agent-preflight` fails 11, set-identical to a clean `fafa16f0` baseline. Spec PR open; implementation PR follows. |