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2 changes: 1 addition & 1 deletion .agents/NOW.md
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@@ -1,6 +1,6 @@
# NOW — the one-Read resume surface

<!-- now-updated: 2026-08-11 -->
<!-- now-updated: 2026-08-12 -->

Snapshot, not log. History is git; evidence:
[parity ledger](parity-ledger.md), and benchmarks. Budget: 100 lines / 6,000
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1 change: 1 addition & 0 deletions .agents/coordination.md
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Expand Up @@ -1993,6 +1993,7 @@ this claim will meet. The tiled row is speed-gatable on dgx.
| `CLAIM-ENG-LOAD-DIRECT-UPLOAD` | `ENG-LOAD-DIRECT-UPLOAD` (engine-matrix, NEW row -> `ACTIVE`) | Claude Code (opus-5) | isolated worktree `.claude/worktrees/agent-a122a5ddc3546bf31`; GB10 `dgx.casa` tree `~/work/load150/src` (Vulkan `build-vk` + CUDA `build-cuda`), every GPU stage under `flock $HOME/gpu.lock`, `local-ai-worker` parked and restored | branch `row/ENG-LOAD-DIRECT-UPLOAD`, base `origin/main` `375a471e` | Issue #150. Owns ONLY: the refcounted safetensors mapping + byte counters (`include/vllm/model_executor/model_loader/safetensors_reader.h`, `src/vllm/model_executor/model_loader/safetensors_reader.cpp`), `BorrowStTensorBytes` + the `AdoptDeviceBytesAsHost` mmap branch + `OwnedTensor::mmap_src` (`include/vllm/model_executor/models/qwen3_5_weights.h`, `src/vllm/model_executor/models/qwen3_5_weights.cpp`), the qualifying call sites in `include/vllm/model_executor/models/dense_weight_loaders.h` and `src/vllm/model_executor/models/qwen3_5_dense_weights.cpp`, the upload counter in `include/vllm/model_executor/models/dense_attn_block.h`, the `VT_LOAD_STATS` phase timing in `src/vllm/entrypoints/model_loader.cpp`, NEW `tests/vllm/test_load_direct_upload.cpp` + its `tests/CMakeLists.txt` line, NEW `.agents/specs/load-direct-upload.md`, the NEW engine-matrix row + its Loading/Total rollup, the `#150` roadmap intake cell, two `docs/ENVIRONMENT.md` rows, this claim, `.agents/NOW.md`, and the `docs/STATUS.md`/`docs/BENCHMARKS.md` one-liners. **NON-COLLISION:** no new kernel, no model registry change, no CMake target change beyond one test line; every non-verbatim loader helper is untouched and the lever is same-binary A/B-able (`VT_LOAD_DIRECT_UPLOAD=0`). MUST NOT touch README, Metal/SACRED/apex/darwin, or any model/kernel source | `ACTIVE` | 2026-08-09 — mechanism test 6/6 (77) and RED under two mutations; GB10 Vulkan gates on the changed tree green (`test_vulkan_backend` 35/35·2650, `test_backend_cross_device` 11/11·132, `test_opt_paged_engine` 6/6 prompts token-exact 96/96, 0 declines, device type 3); GB10 CUDA full `ctest` 383/393 with BOTH SACRED gates PASS and all 10 failures reproduced on a clean `origin/main` build; 27B bf16 load 1.54x warm / 1.61x cold, bytes moved 100.196 -> 81.260 GiB; `local-ai-worker` restored (`--restart=always`, Up). Fresh scoped review OWED |
| `CLAIM-ENG-RELEASE-CONTAINERS-W1-W7` | `ENG-RELEASE-CONTAINERS` (`INVENTORIED`->`READY`->`ACTIVE`; spike spec + W1-W5/W7) | Claude Code (opus-5), helper role | isolated worktree `/home/mudler/_git/vllm.cpp-containers`; local Docker only -- NO GPU, NO registry push, NO publication | `row/ENG-RELEASE-CONTAINERS`, base `origin/main` `24306364`, PR [#307](https://github.com/mudler/vllm.cpp/pull/307) | Container spike spec, `docker/Dockerfile` (cpu/vulkan/cuda calling the release scripts), container matrix + checker, image validator, workflow + least-privilege guard, and the SIGTERM fix the boot gate surfaced (#312). Excludes W6 matching-hardware runtime evidence and any GHCR publication | `ACTIVE` | 2026-08-10 -- cpu lane built and gated e2e (config+layout+boot, clean SIGTERM 0.25 s, RED 137 before the fix); mutation suites 31/31 and 22/22; cuda/vulkan gated statically but never built here; nothing published |
| `CLAIM-ROCM-GDN-KERNELS` | `BACKEND-ROCM` (stays `ACTIVE` — M3 GDN kernel slice, issue #41) | pi (kimi-k3) | isolated worktree `/home/vikash/vllm.cpp-rocm-gdn-kernels`, base `origin/main` `5812b8b6`; 4x RX 7900 XTX gfx1100 discrete, ROCm 7.14, GPU jobs hold `~/gpu.lock` | `row/ROCM-GDN-KERNELS` | The M3 GDN kernel family unblocking Qwen3.5-0.8B M2 on discrete ROCm. Owns ONLY: NEW `.agents/specs/rocm-gdn-kernels.md`; NEW `src/vt/rocm/rocm_gdn.hip` (10 ops: kGdnStateGather/Scatter 77/78, kCausalConv1dFwd/Update 5/6, kRmsNormGated 9, kSigmoidGateBf16 58, kGdnPrefill/Decode 10/11, kGdnPostConv 65, kAttnQkNormRopeGate 67 — hand-translated from `src/vt/cuda/cuda_gdn.cu`/`cuda_ops.cu` donors); ADDITIVE registration entries in `src/vt/rocm/rocm_ops.hip`; ADDITIVE GDN cases + buffer helpers in `tests/vt/test_backend_cross_device.cpp`; this claim + `.agents/NOW.md`. **NON-COLLISION:** every new file is ROCm-only; the two shared-file edits are additive registration/case blocks that change no existing behavior (unregistered-op backends skip; CUDA/CPU/Vulkan paths byte-identical). Disjoint from #234 (sampling), #317 (gemma4 FP8/WMMA), #273 (near-tie docs). | `ACTIVE` | 2026-08-11 — **ALL 5 FAMILIES LANDED AS STACKED DRAFT PRs + M2 E2E COMPLETE.** #334 (spec + state I/O), #336 (conv), #341 (postconv), #343 (recurrence), #345 (norm-gate/preamble + the SupportsCompressedGdnState capability seam). Qwen3.5-0.8B runs e2e all-native on discrete gfx1100, deterministic; 'The sky is' 8/8 CPU parity; open-prompt divergence characterized as not-state-rounding, GDN-path drift analysis named open. Gates per family: cross-device green (162/162 total), focused 3/3, full-suite zero-delta vs base. NEXT: fresh review + operator gate per PR; then the MoeRouterTopK bf16-logits arm (the named MoE-path blocker) and the GDN-path divergence characterization. |
| `CLAIM-ROCM-M4` | `BACKEND-ROCM` (stays `ACTIVE` — M4 correctness gate on gfx1100, issue #41) | pi (kimi-k3) | isolated worktree `/home/vikash/vllm.cpp-rocm-m4`, base `origin/main` `8b00f79f`; 4x RX 7900 XTX gfx1100 discrete, ROCm 7.14, GPU jobs hold `~/gpu.lock`; the pinned vLLM-ROCm oracle runs in the committed container image `vllm-rocm-oracle:555967922-gfx1100` | `row/ROCM-M4-GATE` | The M4 gate: the pinned vLLM-ROCm oracle on gfx1100 + the ROCm device-golden lane in the Qwen3-0.6B near-tie gate. Owns ONLY: NEW `.agents/specs/rocm-m4-oracle.md` (oracle build/capture/gate recipe); ADDITIVE `kROCM` arm in `tests/parity/test_qwen3_paged_engine.cpp` (the existing Metal/Tenstorrent device-golden lane extended, no CUDA/CPU/Metal/TT behaviour change); NEW goldens `tests/parity/goldens/qwen3_greedy_0_6b/{our_ids_rocm.npy,neartie_gap_mnats_rocm.npy,greedy_ids_rocm.npy,greedy_dist_rocm.npy}` (dgx base byte-untouched); this claim + `.agents/NOW.md` + `parity-ledger` row + `docs/STATUS.md`. **NON-COLLISION:** the gate edit is a three-branch ternary extension already established for two other devices; the goldens are additive files; disjoint from the in-flight kernel PRs (#497/#506/#509/#523) which touch no parity-gate file. | `ACTIVE` | 2026-08-12 — **M4 GATE LANDED GREEN.** Oracle built from source at pin `555967922` in `rocm/vllm-dev:base` (wheel `0.23.1rc1.dev1511+g555967922.rocm723`, `_rocm_C` ABI present; runtime identity string verified == the parity-pin block), K=10 per-prompt greedy capture DETERMINISTIC in every (prompt,pos) cell. Our engine vs the SAME-BOX oracle: **16/16 prompts PASS** (STRICT token-exact 11/16, near-tie-band 5/16, max gap 0.125 nats @ prompt[3] tok1, 0 forward-divergent; 125/125 assertions), BACKEND PROOF kPagedAttention selections 7,168 / 0 declines on device type 5. The known p0 France/Italy flip is a literal 0.0000-nat tie in the oracle's own logits (Metal-lane M3b signature, reproduced on ROCm). **0.8B GDN LANE LANDED AS THE RED ANCHOR (stacked branch `row/ROCM-M4-GDN-GATE`):** NEW `tests/parity/test_qwen35_paged_engine.cpp` — the oracle-backed near-tie gate for Qwen3.5-0.8B — **FAILS 13/16 at landing by design** (0/16 strict, 3/16 band, max teacher-forced gap 14.125 nats; first-token divergences on 6 prompts; backend proof GREEN: 15/15 GDN ops dispatch, 0 declines). The known 0.8B CPU/ROCm divergence is now oracle-measured as a REAL forward divergence, not a near-tie; the gate is the committed RED test the forward fix turns GREEN. Goldens carry manifest.json (oracle identity + pinned HF revision 2fc06364 via `parity::HfSnapshot`; check-snapshot-pins clean). NEXT: the 0.8B forward fix (the RED anchor's target), then the 35B keep-quant gate; fresh review + operator gate for both PRs. |
**CLOSED same-session claim — `CLAIM-TP-SPIKE-287` (task #287, 2026-08-08,
records-only, helper `row/SPIKE-TENSOR-PARALLELISM` draft PR #143, base
`b38f78a7`).** Not an active-claims row because every referenced row keeps its
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