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1. QPulse-Tiny-ECG-classifier-ASIC QPulse-Tiny-ECG-classifier-ASIC Public

   My AUC Silicon Sprint Project a tiny 1D-CNN accelerator generated via the HLS4ML Library, taped out in Sky Water 130nm using LibreLane

   Verilog

2. Elastic-Buffer-Design-UVM-Verification Elastic-Buffer-Design-UVM-Verification Public

   An Elastic Buffer Design and a UVM Verification environment for verifying USB 3 Gen 1 EB

   SystemVerilog 1

3. DSP_Custom_AXI_IPs DSP_Custom_AXI_IPs Public

   Custom AXI FIR IP Tested on Avnet U96 Zynq MPSoC kit

   SystemVerilog 3

4. ODE_solver_NIOS_II ODE_solver_NIOS_II Public

   NIOS II controlled hardware ODE solver implemented on Cyclone IV FPGA

   Verilog

5. Matrix-Inversion-processor Matrix-Inversion-processor Public

   MATLAB

6. pyuvm-asyncio-HIL pyuvm-asyncio-HIL Public

   Forked from pyuvm/pyuvm

   PyUVM decoupled from cocotb, patched with asyncio to be used for Hardware-In-Loop HIL testing

   Python