RISC 5-stage 16-bit piplined processor with harvard architecture. And assembler to decode instructions to machine code.
| One Operand Instructions | Two Operand Instructions | Memory Instructions | Branch Instructions |
|---|---|---|---|
| NOP | MOV Rsrc, Rdst | PUSH Rsrc | JZ Rdst |
| HLT | ADD Rdst, Rsrc1, Rsrc2 | POP Rdst | JC Rdst |
| SETC | SUB Rdst, Rsrc1, Rsrc2 | LDM Rdst, Imm | JN Rdst |
| NOT Rdst | AND Rdst, Rsrc1, Rsrc2 | LDD Rdst, offset(Rsrc) | JMP Rdst |
| INC Rdst | IADD Rdst, Rsrc1, Imm | STD Rsrc1, offset(Rsrc2) | CALL Rdst |
| OUT Rsrc | - | - | RET (for call) |
| IN Rdst | - | - | INT index |
| - | - | - | RTI (for interrupt) |
| 5-bits Opcode | 3-bit src1 register address | 3-bit src2 register address | 3-bit dst register address | 2-bit (not yet used) |
|---|
more detailed document for decoding the instructions click
