RISC-V Pipelined Processor Front-End Implementation

This repository contains the implementation of the front-end (Instruction Fetch and Instruction Decode stages) of a 5-stage pipelined RISC-V processor, specifically adhering to the RV32I instruction set extension (32-bit data and instructions, integer arithmetic/logic operations only).

The implementation follows the principles outlined in the course laboratory work (Lucrarea 2).

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Project Overview

The front-end is composed of the Instruction Fetch (IF) and Instruction Decode (ID) pipeline stages, as illustrated in the overall block diagram .

Pipeline Stages

The full 5-stage pipeline is:

1. IF (Instruction Fetch): Read the current instruction.
2. ID (Instruction Decode): Decode the instruction and read register operands.
3. EX (Execute): Execute the instruction.
4. MEM (Memory): Data memory read/write operations.
5. WB (Write Back): Write final results back to the registers.

Implementation Scope (IF + ID)

This project focuses on implementing the IF and ID stages, including the modules defined below. Note that certain control signals (e.g., PC_Write, IF_ID_Write, PC_Branch, PCSrc, RD_WB, RegWrite_WB, ALU_DATA_WB) are generated by future stages (e.g., Hazard Detection Unit in EX stage) and are simulated in the testbench for functional testing of the front-end.

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🛠️ Module Implementations

1. Instruction Fetch (IF) Modules

These modules comprise the Instruction Fetch stage (Fig. 2 in the source document).

Module Name	Description	Ports
mux2_1	2-to-1 Multiplexer for selecting the next PC value (PC+4 or PC_Branch)	ina, inb, sel, out
PC	Program Counter (D-type Register)	clk, res, write, in, out
instruction_memory	Instruction Memory (Asynchronous Read)	address ([9:0]), instruction ([31:0])
adder	32-bit Adder (for PC+4 calculation)	ina, inb, out
IF	Top module for the IF stage, connecting all IF modules	clk, reset, PCSrc, PC_write, PC_Branch, PC_IF, INSTRUCTION_IF

Note on instruction_memory addressing: The PC is incremented by 4 (bytes), but since the memory word is 32 bits (4 bytes), the address needs to be shifted right by 2 (divided by 4) to access consecutive instructions stored on consecutive memory lines. The address input address[9:0] is PC[11:2].

2. Instruction Decode (ID) Modules

These modules are implemented as part of the Instruction Decode stage (Fig. 3 in the source document).

Module Name	Description	Ports
registers	RISC-V Register Bank (32 x 32-bit registers, x0 is hardwired to 0)	clk, reg_write, read_reg1, read_reg2, write_reg, write_data, read_data1, read_data2
imm_gen	Immediate Value Generator	in (INSTRUCTION_ID), out (IMM_ID)
ID	Top module for the ID stage, connecting the Register Bank and Immediate Generator	clk, PC_ID, INSTRUCTION_ID, RegWrite_WB, ALU_DATA_WB, RD_WB, outputs for IMM, data, funct fields, etc.

Immediate Generation: The imm_gen module must implement the logic for extracting and sign-extending the immediate values for the following instruction types: I-type (lw, addi, andi, ori, xori, slti, sltiu, srli, srai, slli), S-type (sw), B-type (beq, bne, blt, bge, bltu, bgeu), U-type, and J-type (although specific U/J instructions aren't listed, the formats exist). Refer to the instruction formats (R, I, S, B, U, J types) for bit field extraction and assembly .

3. Pipeline Register

Module Name	Description	Ports
IF_ID	Pipeline register separating the IF and ID stages	Standard synchronous register ports for passing PC_out and INSTRUCTION_out from IF to ID.

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🔗 Top-Level Module

The RISC_V_IF_ID module connects the IF stage, the IF_ID pipeline register, and the ID stage to form the complete front-end.

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📝 Test Instructions

1. Encoding Test Instructions

The following RISC-V instructions were encoded (as 32-bit hexadecimal values) to test the functionality, particularly the Register File read and the Immediate Generator in the ID stage.

Instruction	Type	Assembly	Hex Encoding (Example)
add	R	add x2, x1, x0	00008133
addi	I	addi x1, x1, 1	00108093
and	R	and x3, x1, x2	0020f1b3
ori	I	ori x4, x1, 1	0010e213
sw	S	sw x4, 4(x5)	004222a3
lw	I	lw x12, 8(x0)	00802683
beq	B	beq x18, x0, 5c	05c90463

2. Simulation

Use the provided testbench file (ID.v is referenced for ID module) to simulate the design. The expected output is a waveform similar to the one provided in the figures . Ensure the Register File is initialized with values from 0 to 31 before the test.