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[entropy source, dv] Entropy source vendoring#594

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csabakiss-semify:csk_entropy_source_vendoring
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[entropy source, dv] Entropy source vendoring#594
csabakiss-semify wants to merge 2 commits into
lowRISC:mainfrom
csabakiss-semify:csk_entropy_source_vendoring

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This is a PR about the entropy source block level DV vendoring.

Linked to issue #429

@csabakiss-semify csabakiss-semify changed the title Csk entropy source vendoring [entropy source, dv] Entropy source vendoring Jun 2, 2026
Comment thread hw/vendor/patches/lowrisc_ip/entropy_src/0002_Fix_DV_Paths.patch
Signed-off-by: Csaba Kiss <csaba.kiss@semify-eda.com>
@csabakiss-semify csabakiss-semify force-pushed the csk_entropy_source_vendoring branch from 7de4a9d to f0ef614 Compare June 4, 2026 09:44
Comment thread hw/top_chip/dv/mocha_sim_cfgs.hjson Outdated
Signed-off-by: Csaba Kiss <csaba.kiss@semify-eda.com>
@csabakiss-semify csabakiss-semify force-pushed the csk_entropy_source_vendoring branch from f0ef614 to f6b59a2 Compare June 5, 2026 11:08
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This PR LGTM, thanks Csaba.

The results we are getting on this branch are in line with OpenTitan results for a full regression (below is coming from this branch):

|  Stage  |                   Name                    | Tests                                  |  Max Job Runtime  |  Simulated Time  |  Passing  |  Total  |  Pass Rate  |
|:-------:|:-----------------------------------------:|:---------------------------------------|:-----------------:|:----------------:|:---------:|:-------:|:-----------:|
|   V1    |                   smoke                   | entropy_src_smoke                      |      4.000s       |     54.904us     |    50     |   50    |  100.00 %   |
|   V1    |               csr_hw_reset                | entropy_src_csr_hw_reset               |      2.000s       |     25.535us     |     5     |    5    |  100.00 %   |
|   V1    |                  csr_rw                   | entropy_src_csr_rw                     |      2.000s       |     75.271us     |    20     |   20    |  100.00 %   |
|   V1    |               csr_bit_bash                | entropy_src_csr_bit_bash               |      26.000s      |    879.206us     |     5     |    5    |  100.00 %   |
|   V1    |               csr_aliasing                | entropy_src_csr_aliasing               |      6.000s       |    381.436us     |     5     |    5    |  100.00 %   |
|   V1    |        csr_mem_rw_with_rand_reset         | entropy_src_csr_mem_rw_with_rand_reset |      5.000s       |    102.535us     |     9     |   20    |   45.00 %   |
|   V1    | regwen_csr_and_corresponding_lockable_csr | entropy_src_csr_rw                     |      2.000s       |     75.271us     |    20     |   20    |  100.00 %   |
|   V1    | regwen_csr_and_corresponding_lockable_csr | entropy_src_csr_aliasing               |      6.000s       |    381.436us     |     5     |    5    |  100.00 %   |
|   V1    |                                           | **TOTAL**                              |                   |                  |    94     |   105   |   89.52 %   |
|   V2    |                 firmware                  | entropy_src_smoke                      |      4.000s       |     54.904us     |    50     |   50    |  100.00 %   |
|   V2    |                 firmware                  | entropy_src_rng                        |     859.000s      |   14020.890us    |    288    |   300   |   96.00 %   |
|   V2    |                 firmware                  | entropy_src_fw_ov                      |     942.000s      |   14082.965us    |    266    |   300   |   88.67 %   |
|   V2    |               firmware_mode               | entropy_src_fw_ov                      |     942.000s      |   14082.965us    |    266    |   300   |   88.67 %   |
|   V2    |                 rng_mode                  | entropy_src_rng                        |     859.000s      |   14020.890us    |    288    |   300   |   96.00 %   |
|   V2    |               rng_max_rate                | entropy_src_rng_max_rate               |     1597.000s     |   14019.984us    |    383    |   400   |   95.75 %   |
|   V2    |               health_checks               | entropy_src_rng                        |     859.000s      |   14020.890us    |    288    |   300   |   96.00 %   |
|   V2    |               conditioning                | entropy_src_rng                        |     859.000s      |   14020.890us    |    288    |   300   |   96.00 %   |
|   V2    |                interrupts                 | entropy_src_rng                        |     859.000s      |   14020.890us    |    288    |   300   |   96.00 %   |
|   V2    |                interrupts                 | entropy_src_intr                       |     115.000s      |    504.769us     |    50     |   50    |  100.00 %   |
|   V2    |                  alerts                   | entropy_src_rng                        |     859.000s      |   14020.890us    |    288    |   300   |   96.00 %   |
|   V2    |                  alerts                   | entropy_src_functional_alerts          |      10.000s      |    186.764us     |    50     |   50    |  100.00 %   |
|   V2    |                stress_all                 | entropy_src_stress_all                 |     715.000s      |   14047.920us    |    49     |   50    |   98.00 %   |
|   V2    |             functional_errors             | entropy_src_functional_errors          |     219.000s      |   10011.961us    |    992    |  1000   |   99.20 %   |
|   V2    |     firmware_ov_read_contiguous_data      | entropy_src_fw_ov_contiguous           |      91.000s      |    6562.956us    |    50     |   50    |  100.00 %   |
|   V2    |                 intr_test                 | entropy_src_intr_test                  |      2.000s       |     41.370us     |    50     |   50    |  100.00 %   |
|   V2    |                alert_test                 | entropy_src_alert_test                 |      14.000s      |     55.297us     |    50     |   50    |  100.00 %   |
|   V2    |           tl_d_oob_addr_access            | entropy_src_tl_errors                  |      12.000s      |    1191.674us    |    20     |   20    |  100.00 %   |
|   V2    |            tl_d_illegal_access            | entropy_src_tl_errors                  |      12.000s      |    1191.674us    |    20     |   20    |  100.00 %   |
|   V2    |          tl_d_outstanding_access          | entropy_src_csr_hw_reset               |      2.000s       |     25.535us     |     5     |    5    |  100.00 %   |
|   V2    |          tl_d_outstanding_access          | entropy_src_csr_rw                     |      2.000s       |     75.271us     |    20     |   20    |  100.00 %   |
|   V2    |          tl_d_outstanding_access          | entropy_src_csr_aliasing               |      6.000s       |    381.436us     |     5     |    5    |  100.00 %   |
|   V2    |          tl_d_outstanding_access          | entropy_src_same_csr_outstanding       |      4.000s       |    281.855us     |    20     |   20    |  100.00 %   |
|   V2    |            tl_d_partial_access            | entropy_src_csr_hw_reset               |      2.000s       |     25.535us     |     5     |    5    |  100.00 %   |
|   V2    |            tl_d_partial_access            | entropy_src_csr_rw                     |      2.000s       |     75.271us     |    20     |   20    |  100.00 %   |
|   V2    |            tl_d_partial_access            | entropy_src_csr_aliasing               |      6.000s       |    381.436us     |     5     |    5    |  100.00 %   |
|   V2    |            tl_d_partial_access            | entropy_src_same_csr_outstanding       |      4.000s       |    281.855us     |    20     |   20    |  100.00 %   |
|   V2    |                                           | **TOTAL**                              |                   |                  |   2348    |  2420   |   97.02 %   |
|   V2S   |                tl_intg_err                | entropy_src_sec_cm                     |      4.000s       |    468.949us     |     5     |    5    |  100.00 %   |
|   V2S   |                tl_intg_err                | entropy_src_tl_intg_err                |      8.000s       |    333.210us     |    20     |   20    |  100.00 %   |
|   V2S   |           sec_cm_config_regwen            | entropy_src_rng                        |     859.000s      |   14020.890us    |    288    |   300   |   96.00 %   |
|   V2S   |           sec_cm_config_regwen            | entropy_src_cfg_regwen                 |      3.000s       |     21.733us     |    50     |   50    |  100.00 %   |
|   V2S   |            sec_cm_config_mubi             | entropy_src_rng                        |     859.000s      |   14020.890us    |    288    |   300   |   96.00 %   |
|   V2S   |            sec_cm_config_redun            | entropy_src_rng                        |     859.000s      |   14020.890us    |    288    |   300   |   96.00 %   |
|   V2S   |           sec_cm_intersig_mubi            | entropy_src_rng                        |     859.000s      |   14020.890us    |    288    |   300   |   96.00 %   |
|   V2S   |           sec_cm_intersig_mubi            | entropy_src_fw_ov                      |     942.000s      |   14082.965us    |    266    |   300   |   88.67 %   |
|   V2S   |         sec_cm_main_sm_fsm_sparse         | entropy_src_functional_errors          |     219.000s      |   10011.961us    |    992    |  1000   |   99.20 %   |
|   V2S   |         sec_cm_main_sm_fsm_sparse         | entropy_src_sec_cm                     |      4.000s       |    468.949us     |     5     |    5    |  100.00 %   |
|   V2S   |         sec_cm_ack_sm_fsm_sparse          | entropy_src_functional_errors          |     219.000s      |   10011.961us    |    992    |  1000   |   99.20 %   |
|   V2S   |         sec_cm_ack_sm_fsm_sparse          | entropy_src_sec_cm                     |      4.000s       |    468.949us     |     5     |    5    |  100.00 %   |
|   V2S   |            sec_cm_rng_bkgn_chk            | entropy_src_rng                        |     859.000s      |   14020.890us    |    288    |   300   |   96.00 %   |
|   V2S   |           sec_cm_fifo_ctr_redun           | entropy_src_functional_errors          |     219.000s      |   10011.961us    |    992    |  1000   |   99.20 %   |
|   V2S   |           sec_cm_fifo_ctr_redun           | entropy_src_sec_cm                     |      4.000s       |    468.949us     |     5     |    5    |  100.00 %   |
|   V2S   |             sec_cm_ctr_redun              | entropy_src_functional_errors          |     219.000s      |   10011.961us    |    992    |  1000   |   99.20 %   |
|   V2S   |             sec_cm_ctr_redun              | entropy_src_sec_cm                     |      4.000s       |    468.949us     |     5     |    5    |  100.00 %   |
|   V2S   |           sec_cm_ctr_local_esc            | entropy_src_functional_errors          |     219.000s      |   10011.961us    |    992    |  1000   |   99.20 %   |
|   V2S   |   sec_cm_esfinal_rdata_bus_consistency    | entropy_src_functional_alerts          |      10.000s      |    186.764us     |    50     |   50    |  100.00 %   |
|   V2S   |      sec_cm_tile_link_bus_integrity       | entropy_src_tl_intg_err                |      8.000s       |    333.210us     |    20     |   20    |  100.00 %   |
|   V2S   |                                           | **TOTAL**                              |                   |                  |   1671    |  1725   |   96.87 %   |
|   V3    |           external_health_tests           | entropy_src_rng_with_xht_rsps          |     853.000s      |   14014.334us    |    50     |   50    |  100.00 %   |
|   V3    |                                           | **TOTAL**                              |                   |                  |    50     |   50    |  100.00 %   |
|         |                                           | **TOTAL**                              |                   |                  |   2487    |  2570   |   96.77 %   |

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