Add `mcounteren` register by SamuelRiedel · Pull Request #2403 · lowRISC/ibex

SamuelRiedel · 2026-05-11T08:09:03Z

This PR adds the mcounteren register, which has so far been tied to zero and implements the U-mode performance counter aliases. The mcounteren register can be locked with an external MUBI signal (mcounteren_writable_i).

DV:
This PR adds two directed tests:

mcounteren_test goes through multiple configurations of the mcounteren register and validates that u-mode can only access the ones enabled.
mcounteren_lock_test verifies that the mcounteren CSR cannot be modified without the mcounteren_writable_i signal being set.

To Dos:

For the directed tests and the cosim to pass, we have to update riscv-isa-sim to also support those performance counters: Enable ZIHPM unpriviledged performance counters riscv-isa-sim#29
Currently, u-mode counter reads will lead to illegal instruction exceptions. However, we are not gating the value at the CSR module's interface for simplicity. The signal will not leave the core, but we should double-check that this is no security issue.
The dv/uvm/core_ibex/directed_tests/directed_testlist.yaml changes a lot everytime I regenerate it after even small modifications. This polluted the diff quite a bit. Is this expected?

resolves #1973
fixes #2312

gautschimi

The changes look all good to me! Just a few minor comments. (I did not look at the two WIP commits about formal)

SamuelRiedel · 2026-05-19T15:48:17Z

I disabled the check of the mcounteren CSR in the formal verification for now. Another reason for the failure of the formal verification was that we ran out of memory on the runner that has twice as many cores but half as much memory available. I'll address this in a separate PR and rebase once merged.

gautschimi

Looks good to me!

I mostly looked at RTL, but the changes in python, C, yaml, etc. look also good to me!

The set created a random order of the tests. So small modifications or additions to the testlist polluted the diff. Fixing the order in a list makes the output deterministic. I swapped the order of the tests to match the current output order of the testlist to avoid a diff.

marnovandermaas

Since we're adding an extension do we need to do an update of ISA strings that are passed to compilers?

marnovandermaas · 2026-06-03T15:12:22Z


+  // mcounteren: machine counter enable (controls U-mode counter access)
+  logic [31:0]                 mcounteren;
+  logic [MHPMCounterNum+3-1:0] mcounteren_d, mcounteren_q;


It probably makes sense to have at least a local parameter with the 3 offset since this is shared with the mcountinhibit above.

marnovandermaas · 2026-06-04T08:17:07Z

I double checked this mapping and I think they are right.

marnovandermaas · 2026-06-04T08:23:35Z


  // CPU Control Signals
  input  ibex_mubi_t                                                   fetch_enable_i,
+  input  ibex_mubi_t                                                   mcounteren_writable_i,


What's the point of making this an input as opposed to a parameter? Is there a use-case to be able to switch this dynamically during runtime?

Yes. This allows locking the mcounteren in a certain configuration. For example, the boot code could enable only the instret counter to be accessible to the user mode and then lock it to prevent the software from switching it later and use other counters to profile the core. This option, gives us the most flexibility and security.

marnovandermaas · 2026-06-04T08:26:52Z

 # end up as float otherwise).
 VERILATOR_VERSION=v4.210
-IBEX_COSIM_VERSION=6d5b660
+IBEX_COSIM_VERSION=aadf648


This bump adds ZIHPM extension to Spike but it also pulls in the Zc* extensions. Is there any risk in that inclusion?

You're right. But that will be fine, because we anyway already have the Zc* extension in the RTL. Only the DV is not fully merged yet, but already having Spike support those extensions will not hurt.

marnovandermaas

I realised there are some more commits so here are some more comments. Very good work on this and please disregard my previous mention that the docs needed updating.

marnovandermaas · 2026-06-04T08:29:58Z


    if 'riscv-arch-tests' in test_suite_list or test_suite == 'all':
-        arch_tests = {'rv32i_m/B/src', 'rv32i_m/C/src', 'rv32i_m/I/src', 'rv32i_m/M/src', 'rv32i_m/Zifencei/src'}
+        arch_tests = ['rv32i_m/M/src', 'rv32i_m/C/src', 'rv32i_m/Zifencei/src', 'rv32i_m/I/src',  'rv32i_m/B/src']


Nit extra space here.

marnovandermaas · 2026-06-04T08:32:48Z

Thanks for adding this test, very useful!

marnovandermaas · 2026-06-04T08:34:32Z


+  // Set the value of minstret.
+  //
+  // The co-simulation model doesn't alter the value of minstret itself (other


How come this is true? Spike should have all the information it needs to calculate minstret right?

You're right. And it does, the Spike counter is just lagging one instruction behind Ibex. It should match though, so I'll investigate a bit more...

marnovandermaas · 2026-06-04T08:36:04Z

+  li   s1, 0x0
+  csrw mcounteren, s1
+  csrr t1, mcounteren
+  bne  t1, s0, fail


Should this be s1?

No, because in this instance, the register should be locked. So the csrw mcounteren, s1 must have no effect. So the read should return the previous write value.

marnovandermaas · 2026-06-04T08:36:29Z

+  li   s1, 0x0
+  csrw mcounteren, s1
+  csrr t1, mcounteren
+  bne  t1, s0, fail


Also shouldn't this one fail if it is equal?

Wait, they are both the same lines you commented. So here we either fail if:

The current value is not equal to the previous value (s0=0x5) from before we locked it and tried to change it to s1=0

The current value is equal to s1=0, because this means that the write was successful despite the locking.

I decided to do the first to also catch behaviour where the overwrite had some sort of effect, like changing just a few bits to zero.

marnovandermaas · 2026-06-04T08:38:08Z


 endclass
+
+class core_ibex_mcounteren_lock_test extends core_ibex_base_test;


Thanks for adding this test, this is great!

SamuelRiedel force-pushed the mcounteren branch 4 times, most recently from fcb3067 to bb40866 Compare May 12, 2026 15:51

SamuelRiedel mentioned this pull request May 12, 2026

Enable ZIHPM unpriviledged performance counters lowRISC/riscv-isa-sim#29

Merged

SamuelRiedel force-pushed the mcounteren branch from bb40866 to 797a7d0 Compare May 13, 2026 09:48

SamuelRiedel marked this pull request as ready for review May 13, 2026 09:58

SamuelRiedel requested review from gautschimi, marnovandermaas, nasahlpa and rswarbrick May 13, 2026 09:58

SamuelRiedel force-pushed the mcounteren branch from 797a7d0 to fe78927 Compare May 13, 2026 10:26

andreaskurth requested review from hcallahan-lowrisc and vogelpi May 18, 2026 12:44

SamuelRiedel force-pushed the mcounteren branch from fe78927 to d08633d Compare May 19, 2026 08:57

gautschimi reviewed May 19, 2026

View reviewed changes

Comment thread rtl/ibex_cs_registers.sv

Comment thread rtl/ibex_top.sv

Comment thread dv/uvm/core_ibex/directed_tests/mcounteren_test/mcounteren_test.S

Comment thread dv/uvm/core_ibex/directed_tests/directed_testlist.yaml

SamuelRiedel mentioned this pull request May 20, 2026

[ci] Reduce limit for the formal CI #2438

Merged

SamuelRiedel force-pushed the mcounteren branch from bea655a to 20bcf6a Compare May 28, 2026 14:38

SamuelRiedel mentioned this pull request May 29, 2026

[rv_core_ibex] Add u-mode performance counters and mcounteren lowRISC/opentitan#30135

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3 tasks

gautschimi approved these changes May 29, 2026

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SamuelRiedel added 3 commits June 3, 2026 09:32

[rtl] Add register for mcounteren

6355f79

[rtl] Add unpriviledged counter/timers

72eaebf

[rtl] Add input to lock mcounteren

216c77c

SamuelRiedel force-pushed the mcounteren branch from 20bcf6a to c799da7 Compare June 3, 2026 07:33

SamuelRiedel added 5 commits June 3, 2026 12:09

[ci] Update riscv-isa-sim version

bacacea

[dv] Implement Ibex-specific mcounteren behavior in cosim

497d1ec

[dv] Add mcounteren directed test

791beb6

[dv] Correctly set minstret in cosim

6c1539e

SamuelRiedel added 4 commits June 3, 2026 12:09

[dv] Add directed test for mcounteren lock signal

c27c013

[doc] Document the newly added performance counters

e0d9935

[formal] Exclude u-mode counters from formal verification

37ddcd4

[dv] Check u-mode counter alias the correct m-mode counter

49bffac

SamuelRiedel force-pushed the mcounteren branch from c799da7 to 49bffac Compare June 3, 2026 10:11

marnovandermaas reviewed Jun 4, 2026

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SamuelRiedel mentioned this pull request Jun 5, 2026

[rtl] Fix the minstret counter #2446

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		endclass

		class core_ibex_mcounteren_lock_test extends core_ibex_base_test;

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SamuelRiedel commented May 11, 2026 •

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