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1. RISC-V-32bit-Single-Cycle RISC-V-32bit-Single-Cycle Public

   Verilog

2. PWM_Controller_DeadTime PWM_Controller_DeadTime Public

   Synchronous PWM Generator with Parametric Dead-Time Logic for Power Electronics.

   Verilog

3. SPI_master_slave SPI_master_slave Public

   Robust SPI Master and Slave implementation in Verilog

   Verilog

4. RISCV_memory_mapped_SPI RISCV_memory_mapped_SPI Public

   A custom 32-bit RISC-V CPU integrated with a memory-mapped SPI Master module.

5. 1Bit-SRAM-Custom-IC-Design 1Bit-SRAM-Custom-IC-Design Public

   Transistor-level design and layout of a 1-bit SRAM array column (90nm) with sense amplifier, write driver, and full read/write timing orchestration.