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MiniMax M3: fp8 (e4m3) index-K side cache (+61% long-context decode)#75

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MiniMax M3: fp8 (e4m3) index-K side cache (+61% long-context decode)#75
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@jarrelscy

@jarrelscy jarrelscy commented Jul 5, 2026

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MiniMax M3: fp8 (e4m3) index-K side cache

Summary

Implements the "fp8" arm of the existing indexer_kv_dtype config knob (currently stubbed to bf16-only) for the MiniMax M3 lightning-indexer side cache. Opt-in via --attention-config '{"indexer_kv_dtype": "fp8"}'; default behavior is unchanged.

Motivation

At decode, M3's dominant linear-in-context cost isn't attention — it's the indexer scan: 57 sparse layers each re-read their full per-token index-K side cache every step. At 769K tokens that's 5.6 GB per step in bf16, and _decode_index_score_kernel is DRAM-bandwidth-bound (verified with an L2-resident microbench: the kernel hits 4.2 TB/s when data fits in L2, so bytes are the only lever). fp8 halves the read and also halves the side cache's share of the KV pool.

Why it's safe: the scores only feed a top-k block ranking (the attention itself reads the main KV cache at full fidelity), the scorer takes a max over 128 tokens per block (noise-robust), and index keys are RMS-normed to O(1) magnitudes so a direct e4m3 cast needs no scale factors. DeepSeek V3.2's DSA — the same indexer design lineage — ships fp8 indexer keys natively.

Changes

  • common/indexer.py: accept "fp8"; side cache allocates as float8_e4m3fn.
  • common/ops/index_topk.py: both scorer kernels upcast K loads with .to(q.dtype) — a no-op for bf16 caches (Triton folds it), so existing users are bit-identical.
  • No writer change: the insert paths already cast via .to(idx_cache.dtype) on both the eager and compiled (minimax_m3_sparse_kv_cache_update) paths.
  • New regression test tests/kernels/attention/test_minimax_m3_fp8_indexer.py: fp8-vs-bf16 decode top-k agreement with planted strongly-matching blocks (passes on SM120; block-score correlation vs bf16 measured at 1.0000, top-16 selection differing only on noise-floor ties among random filler blocks).

Measured (4x RTX PRO 6000 Blackwell / SM120, TP4, fp8 main KV, B12X_ATTN, MiniMax-M3-NVFP4, batch 1)

bf16 indexer fp8 indexer
decode @ 6K 12.6 ms/step 12.7 ms/step
decode @ 96K 15.0 ms 14.7 ms
decode @ 384K 25.8 ms (38.8 tok/s) 19.5 ms (51.2 tok/s)
decode @ 769K 42.5 ms (23.5 tok/s) 26.4 ms (37.8 tok/s, +61%)
KV pool @ 1M-token config 1,240K tokens 1,430K tokens

Quality checks on the live server: exact needle retrieval at 751K tokens, coherent generation, vision path unaffected.

Trade-off (stated plainly)

e4m3 adds ~2% relative error to block scores. Since scores only rank blocks, the worst case is an occasional swap at the top-k boundary between blocks whose relevance was already statistically indistinguishable; strongly relevant blocks are unaffected (regression-tested). Not yet covered: task-level long-doc QA benchmarks and spec-decode query lengths > 1 (structurally the same kernels, measured at qlen=1 only). Being opt-in and default-off, users who don't set the flag see zero change.

Context: follow-up to local-inference-lab/sparkinfer#24 (dense split-KV decode fix) — together they take M3 long-context decode on this hardware from ~14 tok/s to ~38 tok/s at 769K tokens.

🤖 Generated with Claude Code

Summary by CodeRabbit

  • New Features

    • Added support for fp8 index-cache storage and selection alongside bf16.
    • Index-scoring now consistently handles cached values in the query’s dtype.
  • Tests

    • Added coverage to verify fp8 top-k block selection closely matches the bf16 reference, including key planted matches.

At decode, the dominant linear-in-context cost for M3 at long context is
the lightning-indexer scan: 57 sparse layers each re-read their full
per-token index-K side cache every step (bf16, 128 B/token/layer -- 5.6 GB
per step at 769K tokens), and the Triton scorer is DRAM-bandwidth-bound.
The scores only feed a top-k block ranking (attention reads the main KV
cache), and index keys are RMS-normed to O(1) magnitudes, so an e4m3 cast
preserves selection while halving the read.

Implements the 'fp8' arm of the existing indexer_kv_dtype config knob:
- side cache allocates as float8_e4m3fn (also halves its KV-pool share)
- the two scorer kernels upcast K loads with .to(q.dtype) -- a no-op for
  bf16 caches, so default behavior is unchanged
- the insert paths already cast via .to(idx_cache.dtype); no writer change

Opt-in via --attention-config '{"indexer_kv_dtype": "fp8"}'.

Measured on 4x RTX PRO 6000 Blackwell (TP4, fp8 main KV, B12X_ATTN, batch 1):
decode 38.8 -> 51.2 tok/s at 384K and 23.5 -> 37.8 tok/s at 769K tokens
(+61%); KV pool at the 1M-token config 1.24M -> 1.43M tokens; short-context
decode unchanged. Needle retrieval verified exact at 751K tokens; fp8-vs-bf16
block-score correlation 1.0000 with top-16 selection agreeing everywhere
above the noise floor (new regression test).

Same design as the fp8 indexer keys DeepSeek V3.2's DSA ships natively.
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Review Change Stack

📝 Walkthrough

Walkthrough

Adds fp8 (float8_e4m3fn) dtype support to the MiniMax M3 indexer cache alongside existing bf16 support, updates dtype validation and implementation-class selection accordingly, casts loaded index-K values to query dtype in Triton kernels, and adds a test verifying fp8 top-k selection matches bf16 reference within tolerance.

Changes

fp8 Indexer Cache Support

Layer / File(s) Summary
Indexer cache dtype validation and selection
vllm/models/minimax_m3/common/indexer.py
MiniMaxM3IndexerCache.__init__ now accepts "fp8" in addition to "bf16", setting storage dtype to torch.float8_e4m3fn for fp8; select_indexer_impl_cls routes both dtypes to the Triton implementation.
Kernel dtype casting for fp8 cache
vllm/models/minimax_m3/common/ops/index_topk.py
Both the paged index block-score kernel and decode index-score kernel cast loaded k values from the index-K cache to q.dtype to correctly handle fp8-stored values.
fp8 vs bf16 top-k agreement test
tests/kernels/attention/test_minimax_m3_fp8_indexer.py
New CUDA-only test plants relevant blocks in a normalized key cache, runs minimax_m3_index_decode against bf16 and fp8 caches, and asserts planted blocks are retained in fp8 results with overlap within tolerance.

Estimated code review effort: 2 (Simple) | ~12 minutes

Sequence Diagram(s)

Not applicable — changes are localized dtype handling and casting logic without multi-component orchestration warranting a sequence diagram.

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✅ Passed checks (5 passed)
Check name Status Explanation
Description Check ✅ Passed Check skipped - CodeRabbit’s high-level summary is enabled.
Title check ✅ Passed The title clearly summarizes the main change: adding fp8 (e4m3) support to the MiniMax M3 index-K side cache.
Docstring Coverage ✅ Passed No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.
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🧹 Nitpick comments (1)
tests/kernels/attention/test_minimax_m3_fp8_indexer.py (1)

1-67: 📐 Maintainability & Code Quality | 🔵 Trivial | ⚡ Quick win

Missing coverage for the prefill/block-score kernel (_index_block_score_kernel).

This test only exercises minimax_m3_index_decode (the decode-side kernel). The PR also modifies _index_block_score_kernel's K-load cast (used for prefill/chunked-prefill scoring), which has no corresponding fp8-vs-bf16 regression test here.

Consider adding an analogous test that plants strongly-matching blocks and asserts prefill block-score top-k agreement between bf16 and fp8 caches, mirroring this test's structure. Want me to draft it?

🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@tests/kernels/attention/test_minimax_m3_fp8_indexer.py` around lines 1 - 67,
Add coverage for the prefill-side fp8 path that is currently untested: this test
only exercises minimax_m3_index_decode, but the change also affects
_index_block_score_kernel. Add an analogous regression test in
test_minimax_m3_fp8_indexer.py that uses the same planted-block setup, runs the
prefill/block-score path against bf16 and fp8 caches, and asserts the top-k
block selection matches closely enough. Reference minimax_m3_index_decode and
_index_block_score_kernel when wiring the new helper so both decode and prefill
scoring are covered.
🤖 Prompt for all review comments with AI agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

Nitpick comments:
In `@tests/kernels/attention/test_minimax_m3_fp8_indexer.py`:
- Around line 1-67: Add coverage for the prefill-side fp8 path that is currently
untested: this test only exercises minimax_m3_index_decode, but the change also
affects _index_block_score_kernel. Add an analogous regression test in
test_minimax_m3_fp8_indexer.py that uses the same planted-block setup, runs the
prefill/block-score path against bf16 and fp8 caches, and asserts the top-k
block selection matches closely enough. Reference minimax_m3_index_decode and
_index_block_score_kernel when wiring the new helper so both decode and prefill
scoring are covered.

ℹ️ Review info
⚙️ Run configuration

Configuration used: Organization UI

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Run ID: fe8808fc-46c9-40ff-b8c8-5e80b9a30af4

📥 Commits

Reviewing files that changed from the base of the PR and between 156b126 and 6a70b2c.

📒 Files selected for processing (3)
  • tests/kernels/attention/test_minimax_m3_fp8_indexer.py
  • vllm/models/minimax_m3/common/indexer.py
  • vllm/models/minimax_m3/common/ops/index_topk.py

@jarrelscy

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Context worth knowing before review: upstream vllm-project merged fp8 indexer-cache support in vllm-project#45892 (2026-06-23), but it is SM100-only — fp8 routes through the fmha_sm100 MSA score path, and select_indexer_impl_cls still raises NotImplementedError for fp8 on the Triton fallback that every non-SM100 GPU uses (SM120 consumer Blackwell, AMD).

This PR is the complementary piece: fp8 support in the Triton indexer impl itself (upcast in both scorer kernels; bf16 behavior bit-identical), so fp8 index caches work on SM120. If you'd rather rebase this tree past vllm-project#45892 first, this patch applies cleanly on top of it too — the guard/upcast sites are the same — and I'm happy to rework it as an upstream vllm-project PR instead if that ordering suits you better.

Measured numbers in the description are from 4x RTX PRO 6000 (SM120), where the upstream MSA fp8 path isn't available.

@jarrelscy

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Upstream version submitted: vllm-project#47665 (Triton-impl fp8 enablement on top of vllm-project#45892's SM100 path, with the decode kernel made robust to Triton front-ends that reject fp8 dot operands). If that lands and this tree rebases past it, this PR becomes unnecessary — feel free to close in favor of the upstream route, or keep this as the interim patch for the current tree.

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